DRAMCtrl.py revision 9489
1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37# Ani Udipi 38 39from m5.params import * 40from AbstractMemory import * 41 42# Enum for memory scheduling algorithms, currently First-Come 43# First-Served and a First-Row Hit then First-Come First-Served 44class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 45 46# Enum for the address mapping, currently corresponding to either 47# optimising for sequential accesses hitting in the open row, or 48# striping across banks. 49class AddrMap(Enum): vals = ['openmap', 'closemap'] 50 51# Enum for the page policy, either open or close. 52class PageManage(Enum): vals = ['open', 'close'] 53 54# SimpleDRAM is a single-channel single-ported DRAM controller model 55# that aims to model the most important system-level performance 56# effects of a DRAM without getting into too much detail of the DRAM 57# itself. 58class SimpleDRAM(AbstractMemory): 59 type = 'SimpleDRAM' 60 cxx_header = "mem/simple_dram.hh" 61 62 # single-ported on the system interface side, instantiate with a 63 # bus in front of the controller for multiple ports 64 port = SlavePort("Slave port") 65 66 # the basic configuration of the controller architecture 67 write_buffer_size = Param.Unsigned(32, "Number of read queue entries") 68 read_buffer_size = Param.Unsigned(32, "Number of write queue entries") 69 70 # threshold in percent for when to trigger writes and start 71 # emptying the write buffer as it starts to get full 72 write_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 73 74 # scheduler, address map and page policy 75 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 76 addr_mapping = Param.AddrMap('openmap', "Address mapping policy") 77 page_policy = Param.PageManage('open', "Page closure management policy") 78 79 # the physical organisation of the DRAM 80 lines_per_rowbuffer = Param.Unsigned("Row buffer size in cache lines") 81 ranks_per_channel = Param.Unsigned("Number of ranks per channel") 82 banks_per_rank = Param.Unsigned("Number of banks per rank") 83 84 # timing behaviour and constraints - all in nanoseconds 85 86 # the amount of time in nanoseconds from issuing an activate command 87 # to the data being available in the row buffer for a read/write 88 tRCD = Param.Latency("RAS to CAS delay") 89 90 # the time from issuing a read/write command to seeing the actual data 91 tCL = Param.Latency("CAS latency") 92 93 # minimum time between a precharge and subsequent activate 94 tRP = Param.Latency("Row precharge time") 95 96 # time to complete a burst transfer, typically the burst length 97 # divided by two due to the DDR bus, but by making it a parameter 98 # it is easier to also evaluate SDR memories like WideIO. 99 # This parameter has to account for bus width and burst length. 100 # Adjustment also necessary if cache line size is greater than 101 # data size read/written by one full burst. 102 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 103 104 # time taken to complete one refresh cycle (N rows in all banks) 105 tRFC = Param.Latency("Refresh cycle time") 106 107 # refresh command interval, how often a "ref" command needs 108 # to be sent. It is 7.8 us for a 64ms refresh requirement 109 tREFI = Param.Latency("Refresh command interval") 110 111 # write-to-read turn around penalty, assumed same as read-to-write 112 tWTR = Param.Latency("Write to read switching time") 113 114 # time window in which a maximum number of activates are allowed 115 # to take place, set to 0 to disable 116 tXAW = Param.Latency("X activation window") 117 activation_limit = Param.Unsigned("Max number of activates in window") 118 119 # Currently rolled into other params 120 ###################################################################### 121 122 # the minimum amount of time between a row being activated, and 123 # precharged (de-activated) 124 # tRAS - assumed to be 3 * tRP 125 126 # tRC - assumed to be 4 * tRP 127 128 # burst length for an access derived from peerBlockSize 129 130# High-level model of a single DDR3 x64 interface (one command and 131# address bus), with default timings based on a DDR3-1600 4 Gbit part, 132# which would amount to 4 Gbyte of memory in 8x8 or 8 GByte in 16x4 133# configuration. 134class SimpleDDR3(SimpleDRAM): 135 # Assuming 64 byte cache lines, use a 2kbyte page size, this 136 # depends on the memory density 137 lines_per_rowbuffer = 32 138 139 # Use two ranks 140 ranks_per_channel = 2 141 142 # DDR3 has 8 banks in all configurations 143 banks_per_rank = 8 144 145 # DDR3-1600 11-11-11 146 tRCD = '13.75ns' 147 tCL = '13.75ns' 148 tRP = '13.75ns' 149 150 # Assuming 64 byte cache lines, across an x64 (8x8 or 16x4) 151 # interface, translates to BL8, 4 clocks @ 800 MHz 152 tBURST = '5ns' 153 154 # DDR3, 4 Gb has a tRFC of 240 CK and tCK = 1.25 ns 155 tRFC = '300ns' 156 157 # DDR3, <=85C, half for >85C 158 tREFI = '7.8us' 159 160 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 161 tWTR = '7.5ns' 162 163 # With a 2kbyte page size, DDR3-1600 lands around 40 ns 164 tXAW = '40ns' 165 activation_limit = 4 166 167 168# High-level model of a single LPDDR2-S4 x64 interface (one 169# command/address bus), with default timings based on a LPDDR2-1066 170# 4Gbit part, which whould amount to 1 GByte of memory in 2x32 or 171# 2GByte in 4x16 configuration. 172class SimpleLPDDR2_S4(SimpleDRAM): 173 # Assuming 64 byte cache lines, use a 2kbyte page size, this 174 # depends on the memory density 175 lines_per_rowbuffer = 32 176 177 # Use two ranks 178 ranks_per_channel = 2 179 180 # LPDDR2-S4 has 8 banks in all configurations 181 banks_per_rank = 8 182 183 # Fixed at 15 ns 184 tRCD = '15ns' 185 186 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 187 tCL = '15ns' 188 189 # Pre-charge one bank 15 ns and all banks 18 ns 190 tRP = '18ns' 191 192 # Assuming 64 byte cache lines, across a x64 interface (2x32 or 193 # 4x16), translates to BL8, 4 clocks @ 533 MHz 194 tBURST = '7.5ns' 195 196 # LPDDR2-S4, 4 Gb 197 tRFC = '130ns' 198 tREFI = '3.9us' 199 200 # Irrespective of speed grade, tWTR is 7.5 ns 201 tWTR = '7.5ns' 202 203 # Irrespective of size, tFAW is 50 ns 204 tXAW = '50ns' 205 activation_limit = 4 206