DRAMCtrl.py revision 10141
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2013 Amin Farmahini-Farahani 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Andreas Hansson 40# Ani Udipi 41 42from m5.params import * 43from AbstractMemory import * 44 45# Enum for memory scheduling algorithms, currently First-Come 46# First-Served and a First-Row Hit then First-Come First-Served 47class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 48 49# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 50# channel, rank, bank, row and column, respectively, and going from 51# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 52# suitable for an open-page policy, optimising for sequential accesses 53# hitting in the open row. For a closed-page policy, RoCoRaBaCh 54# maximises parallelism. 55class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 56 57# Enum for the page policy, either open, open_adaptive or close. 58class PageManage(Enum): vals = ['open', 'open_adaptive', 'close'] 59 60# SimpleDRAM is a single-channel single-ported DRAM controller model 61# that aims to model the most important system-level performance 62# effects of a DRAM without getting into too much detail of the DRAM 63# itself. 64class SimpleDRAM(AbstractMemory): 65 type = 'SimpleDRAM' 66 cxx_header = "mem/simple_dram.hh" 67 68 # single-ported on the system interface side, instantiate with a 69 # bus in front of the controller for multiple ports 70 port = SlavePort("Slave port") 71 72 # the basic configuration of the controller architecture 73 write_buffer_size = Param.Unsigned(32, "Number of write queue entries") 74 read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 75 76 # threshold in percent for when to forcefully trigger writes and 77 # start emptying the write buffer 78 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 79 80 # threshold in percentage for when to start writes if the read 81 # queue is empty 82 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 83 84 # minimum write bursts to schedule before switching back to reads 85 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 86 "switching to reads") 87 88 # scheduler, address map and page policy 89 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 90 addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") 91 page_policy = Param.PageManage('open', "Page closure management policy") 92 93 # enforce a limit on the number of accesses per row 94 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 95 "closing"); 96 97 # pipeline latency of the controller and PHY, split into a 98 # frontend part and a backend part, with reads and writes serviced 99 # by the queues only seeing the frontend contribution, and reads 100 # serviced by the memory seeing the sum of the two 101 static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 102 static_backend_latency = Param.Latency("10ns", "Static backend latency") 103 104 # the physical organisation of the DRAM 105 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 106 "device/chip") 107 burst_length = Param.Unsigned("Burst lenght (BL) in beats") 108 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 109 "device/chip") 110 devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 111 ranks_per_channel = Param.Unsigned("Number of ranks per channel") 112 banks_per_rank = Param.Unsigned("Number of banks per rank") 113 # only used for the address mapping as the controller by 114 # construction is a single channel and multiple controllers have 115 # to be instantiated for a multi-channel configuration 116 channels = Param.Unsigned(1, "Number of channels") 117 118 # timing behaviour and constraints - all in nanoseconds 119 120 # the amount of time in nanoseconds from issuing an activate command 121 # to the data being available in the row buffer for a read/write 122 tRCD = Param.Latency("RAS to CAS delay") 123 124 # the time from issuing a read/write command to seeing the actual data 125 tCL = Param.Latency("CAS latency") 126 127 # minimum time between a precharge and subsequent activate 128 tRP = Param.Latency("Row precharge time") 129 130 # minimum time between an activate and a precharge to the same row 131 tRAS = Param.Latency("ACT to PRE delay") 132 133 # time to complete a burst transfer, typically the burst length 134 # divided by two due to the DDR bus, but by making it a parameter 135 # it is easier to also evaluate SDR memories like WideIO. 136 # This parameter has to account for burst length. 137 # Read/Write requests with data size larger than one full burst are broken 138 # down into multiple requests in the SimpleDRAM controller 139 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 140 141 # time taken to complete one refresh cycle (N rows in all banks) 142 tRFC = Param.Latency("Refresh cycle time") 143 144 # refresh command interval, how often a "ref" command needs 145 # to be sent. It is 7.8 us for a 64ms refresh requirement 146 tREFI = Param.Latency("Refresh command interval") 147 148 # write-to-read turn around penalty, assumed same as read-to-write 149 tWTR = Param.Latency("Write to read switching time") 150 151 # minimum row activate to row activate delay time 152 tRRD = Param.Latency("ACT to ACT delay") 153 154 # time window in which a maximum number of activates are allowed 155 # to take place, set to 0 to disable 156 tXAW = Param.Latency("X activation window") 157 activation_limit = Param.Unsigned("Max number of activates in window") 158 159 # Currently rolled into other params 160 ###################################################################### 161 162 # tRC - assumed to be tRAS + tRP 163 164# A single DDR3 x64 interface (one command and address bus), with 165# default timings based on DDR3-1600 4 Gbit parts in an 8x8 166# configuration, which would amount to 4 Gbyte of memory. 167class DDR3_1600_x64(SimpleDRAM): 168 # 8x8 configuration, 8 devices each with an 8-bit interface 169 device_bus_width = 8 170 171 # DDR3 is a BL8 device 172 burst_length = 8 173 174 # Each device has a page (row buffer) size of 1KB 175 # (this depends on the memory density) 176 device_rowbuffer_size = '1kB' 177 178 # 8x8 configuration, so 8 devices 179 devices_per_rank = 8 180 181 # Use two ranks 182 ranks_per_channel = 2 183 184 # DDR3 has 8 banks in all configurations 185 banks_per_rank = 8 186 187 # DDR3-1600 11-11-11-28 188 tRCD = '13.75ns' 189 tCL = '13.75ns' 190 tRP = '13.75ns' 191 tRAS = '35ns' 192 193 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 194 # Note this is a BL8 DDR device. 195 tBURST = '5ns' 196 197 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 198 tRFC = '300ns' 199 200 # DDR3, <=85C, half for >85C 201 tREFI = '7.8us' 202 203 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 204 tWTR = '7.5ns' 205 206 # Assume 5 CK for activate to activate for different banks 207 tRRD = '6.25ns' 208 209 # With a 2kbyte page size, DDR3-1600 lands around 40 ns 210 tXAW = '40ns' 211 activation_limit = 4 212 213 214# A single DDR3 x64 interface (one command and address bus), with 215# default timings based on DDR3-1333 4 Gbit parts in an 8x8 216# configuration, which would amount to 4 GByte of memory. This 217# configuration is primarily for comparing with DRAMSim2, and all the 218# parameters except ranks_per_channel are based on the DRAMSim2 config 219# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has 220# to be manually set, depending on size of the memory to be 221# simulated. By default DRAMSim2 has 2048MB of memory with a single 222# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2 223class DDR3_1333_x64_DRAMSim2(SimpleDRAM): 224 # 8x8 configuration, 8 devices each with an 8-bit interface 225 device_bus_width = 8 226 227 # DDR3 is a BL8 device 228 burst_length = 8 229 230 # Each device has a page (row buffer) size of 1KB 231 # (this depends on the memory density) 232 device_rowbuffer_size = '1kB' 233 234 # 8x8 configuration, so 8 devices 235 devices_per_rank = 8 236 237 # Use two ranks 238 ranks_per_channel = 2 239 240 # DDR3 has 8 banks in all configurations 241 banks_per_rank = 8 242 243 tRCD = '15ns' 244 tCL = '15ns' 245 tRP = '15ns' 246 tRAS = '36ns' 247 248 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz. 249 # Note this is a BL8 DDR device. 250 tBURST = '6ns' 251 252 tRFC = '160ns' 253 254 # DDR3, <=85C, half for >85C 255 tREFI = '7.8us' 256 257 # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns 258 tWTR = '7.5ns' 259 260 tRRD = '6.0ns' 261 262 tXAW = '30ns' 263 activation_limit = 4 264 265 266# A single LPDDR2-S4 x32 interface (one command/address bus), with 267# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 268# configuration. 269class LPDDR2_S4_1066_x32(SimpleDRAM): 270 # 1x32 configuration, 1 device with a 32-bit interface 271 device_bus_width = 32 272 273 # LPDDR2_S4 is a BL4 and BL8 device 274 burst_length = 8 275 276 # Each device has a page (row buffer) size of 1KB 277 # (this depends on the memory density) 278 device_rowbuffer_size = '1kB' 279 280 # 1x32 configuration, so 1 device 281 devices_per_rank = 1 282 283 # Use a single rank 284 ranks_per_channel = 1 285 286 # LPDDR2-S4 has 8 banks in all configurations 287 banks_per_rank = 8 288 289 # Fixed at 15 ns 290 tRCD = '15ns' 291 292 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 293 tCL = '15ns' 294 295 # Pre-charge one bank 15 ns (all banks 18 ns) 296 tRP = '15ns' 297 298 tRAS = '42ns' 299 300 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 301 # Note this is a BL8 DDR device. 302 # Requests larger than 32 bytes are broken down into multiple requests 303 # in the SimpleDRAM controller 304 tBURST = '7.5ns' 305 306 # LPDDR2-S4, 4 Gbit 307 tRFC = '130ns' 308 tREFI = '3.9us' 309 310 # Irrespective of speed grade, tWTR is 7.5 ns 311 tWTR = '7.5ns' 312 313 # Activate to activate irrespective of density and speed grade 314 tRRD = '10.0ns' 315 316 # Irrespective of density, tFAW is 50 ns 317 tXAW = '50ns' 318 activation_limit = 4 319 320# A single WideIO x128 interface (one command and address bus), with 321# default timings based on an estimated WIO-200 8 Gbit part. 322class WideIO_200_x128(SimpleDRAM): 323 # 1x128 configuration, 1 device with a 128-bit interface 324 device_bus_width = 128 325 326 # This is a BL4 device 327 burst_length = 4 328 329 # Each device has a page (row buffer) size of 4KB 330 # (this depends on the memory density) 331 device_rowbuffer_size = '4kB' 332 333 # 1x128 configuration, so 1 device 334 devices_per_rank = 1 335 336 # Use one rank for a one-high die stack 337 ranks_per_channel = 1 338 339 # WideIO has 4 banks in all configurations 340 banks_per_rank = 4 341 342 # WIO-200 343 tRCD = '18ns' 344 tCL = '18ns' 345 tRP = '18ns' 346 tRAS = '42ns' 347 348 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 349 # Note this is a BL4 SDR device. 350 tBURST = '20ns' 351 352 # WIO 8 Gb 353 tRFC = '210ns' 354 355 # WIO 8 Gb, <=85C, half for >85C 356 tREFI = '3.9us' 357 358 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 359 tWTR = '15ns' 360 361 # Activate to activate irrespective of density and speed grade 362 tRRD = '10.0ns' 363 364 # Two instead of four activation window 365 tXAW = '50ns' 366 activation_limit = 2 367 368# A single LPDDR3 x32 interface (one command/address bus), with 369# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 370# configuration 371class LPDDR3_1600_x32(SimpleDRAM): 372 # 1x32 configuration, 1 device with a 32-bit interface 373 device_bus_width = 32 374 375 # LPDDR3 is a BL8 device 376 burst_length = 8 377 378 # Each device has a page (row buffer) size of 4KB 379 device_rowbuffer_size = '4kB' 380 381 # 1x32 configuration, so 1 device 382 devices_per_rank = 1 383 384 # Use a single rank 385 ranks_per_channel = 1 386 387 # LPDDR3 has 8 banks in all configurations 388 banks_per_rank = 8 389 390 # Fixed at 15 ns 391 tRCD = '15ns' 392 393 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 394 tCL = '15ns' 395 396 tRAS = '42ns' 397 398 # Pre-charge one bank 15 ns (all banks 18 ns) 399 tRP = '15ns' 400 401 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 402 # Note this is a BL8 DDR device. 403 # Requests larger than 32 bytes are broken down into multiple requests 404 # in the SimpleDRAM controller 405 tBURST = '5ns' 406 407 # LPDDR3, 4 Gb 408 tRFC = '130ns' 409 tREFI = '3.9us' 410 411 # Irrespective of speed grade, tWTR is 7.5 ns 412 tWTR = '7.5ns' 413 414 # Activate to activate irrespective of density and speed grade 415 tRRD = '10.0ns' 416 417 # Irrespective of size, tFAW is 50 ns 418 tXAW = '50ns' 419 activation_limit = 4 420