AbstractMemory.py revision 5399 
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
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15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Nathan Binkert
28
29from m5.params import *
30from m5.proxy import *
31from MemObject import *
32
33class PhysicalMemory(MemObject):
34    type = 'PhysicalMemory'
35    port = VectorPort("the access port")
36    range = Param.AddrRange(AddrRange('128MB'), "Device Address")
37    file = Param.String('', "memory mapped file")
38    latency = Param.Latency('1t', "latency of an access")
39    latency_var = Param.Latency('0ns', "access variablity")
40    zero = Param.Bool(False, "zero initialize memory")
41
42class DRAMMemory(PhysicalMemory):
43    type = 'DRAMMemory'
44    # Many of these should be observed from the configuration
45    cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed")
46    mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)")
47    mem_actpolicy = Param.String("open", "Open/Close policy")
48    memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
49    bus_width = Param.Int(16, "")
50    act_lat = Param.Latency("2ns", "RAS to CAS delay")
51    cas_lat = Param.Latency("1ns", "CAS delay")
52    war_lat = Param.Latency("2ns", "write after read delay")
53    pre_lat = Param.Latency("2ns", "precharge delay")
54    dpl_lat = Param.Latency("2ns", "data in to precharge delay")
55    trc_lat = Param.Latency("6ns", "row cycle delay")
56    num_banks = Param.Int(4, "Number of Banks")
57    num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")
58
59