xref: /gem5/src/learning_gem5/part2/SimpleMemobj.py

# -*- coding: utf-8 -*-
# Copyright (c) 2017 Jason Lowe-Power
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# Authors: Jason Lowe-Power

from m5.params import *
from m5.SimObject import SimObject

class SimpleMemobj(SimObject):
    type = 'SimpleMemobj'
    cxx_header = "learning_gem5/part2/simple_memobj.hh"

    inst_port = SlavePort("CPU side port, receives requests")
    data_port = SlavePort("CPU side port, receives requests")
    mem_side = MasterPort("Memory side port, sends requests")