xref: /gem5/src/learning_gem5/part2/SimpleCache.py

# -*- coding: utf-8 -*-
# Copyright (c) 2017 Jason Lowe-Power
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# modification, are permitted provided that the following conditions are
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# Authors: Jason Lowe-Power

from m5.params import *
from m5.proxy import *
from MemObject import MemObject

class SimpleCache(MemObject):
    type = 'SimpleCache'
    cxx_header = "learning_gem5/part2/simple_cache.hh"

    # Vector port example. Both the instruction and data ports connect to this
    # port which is automatically split out into two ports.
    cpu_side = VectorSlavePort("CPU side port, receives requests")
    mem_side = MasterPort("Memory side port, sends requests")

    latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss")

    size = Param.MemorySize('16kB', "The size of the cache")

    system = Param.System(Parent.any, "The system this cache is part of")