system_events.cc revision 2683
12158SN/A/*
22158SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
32158SN/A * All rights reserved.
42158SN/A *
52158SN/A * Redistribution and use in source and binary forms, with or without
62158SN/A * modification, are permitted provided that the following conditions are
72158SN/A * met: redistributions of source code must retain the above copyright
82158SN/A * notice, this list of conditions and the following disclaimer;
92158SN/A * redistributions in binary form must reproduce the above copyright
102158SN/A * notice, this list of conditions and the following disclaimer in the
112158SN/A * documentation and/or other materials provided with the distribution;
122158SN/A * neither the name of the copyright holders nor the names of its
132158SN/A * contributors may be used to endorse or promote products derived from
142158SN/A * this software without specific prior written permission.
152158SN/A *
162158SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172158SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182158SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192158SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202158SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212158SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222158SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232158SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242158SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252158SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262158SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Lisa Hsu
292760Sbinkertn@umich.edu *          Nathan Binkert
302158SN/A */
312158SN/A
323567Sgblack@eecs.umich.edu#include "cpu/base.hh"
333567Sgblack@eecs.umich.edu#include "cpu/thread_context.hh"
342432SN/A#include "kern/kernel_stats.hh"
352158SN/A#include "kern/system_events.hh"
363536Sgblack@eecs.umich.edu#include "sim/system.hh"
372215SN/A
382158SN/Ausing namespace TheISA;
392158SN/A
402158SN/Avoid
412521SN/ASkipFuncEvent::process(ThreadContext *tc)
424762Snate@binkert.org{
432158SN/A    Addr newpc = tc->readIntReg(ReturnAddressReg);
442158SN/A
452158SN/A    DPRINTF(PCEvent, "skipping %s: pc=%x, newpc=%x\n", description,
462158SN/A            tc->readPC(), newpc);
472158SN/A
482158SN/A    tc->setPC(newpc);
492158SN/A    tc->setNextPC(tc->readPC() + sizeof(TheISA::MachInst));
502158SN/A/*
512158SN/A    BranchPred *bp = tc->getCpuPtr()->getBranchPred();
522158SN/A    if (bp != NULL) {
532158SN/A        bp->popRAS(tc->getThreadNum());
542158SN/A    }
552158SN/A*/
562158SN/A}
572158SN/A
582158SN/A
594762Snate@binkert.orgFnEvent::FnEvent(PCEventQueue *q, const std::string &desc, Addr addr,
602158SN/A                 Stats::MainBin *bin)
614762Snate@binkert.org    : PCEvent(q, desc, addr), _name(desc), mybin(bin)
622158SN/A{
632158SN/A}
644762Snate@binkert.org
652158SN/Avoid
664762Snate@binkert.orgFnEvent::process(ThreadContext *tc)
672158SN/A{
682158SN/A    if (tc->misspeculating())
692158SN/A        return;
702521SN/A
712521SN/A    tc->getSystemPtr()->kernelBinning->call(tc, mybin);
722158SN/A}
732158SN/A
742158SN/Avoid
752158SN/AIdleStartEvent::process(ThreadContext *tc)
762158SN/A{
772158SN/A    if (tc->getKernelStats())
782158SN/A        tc->getKernelStats()->setIdleProcess(
792158SN/A            tc->readMiscReg(AlphaISA::IPR_PALtemp23), tc);
802158SN/A    remove();
812158SN/A}
822158SN/A
832158SN/Avoid
842158SN/AInterruptStartEvent::process(ThreadContext *tc)
852158SN/A{
862158SN/A    if (tc->getKernelStats())
872158SN/A        tc->getKernelStats()->mode(Kernel::interrupt, tc);
882158SN/A}
892158SN/A
902158SN/Avoid
912158SN/AInterruptEndEvent::process(ThreadContext *tc)
922158SN/A{
932158SN/A    // We go back to kernel, if we are user, inside the rti
942158SN/A    // pal code we will get switched to user because of the ICM write
952158SN/A    if (tc->getKernelStats())
962158SN/A        tc->getKernelStats()->mode(Kernel::kernel, tc);
972158SN/A}
982158SN/A