system_events.cc revision 2190
12SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282760Sbinkertn@umich.edu 292760Sbinkertn@umich.edu#include "encumbered/cpu/full/cpu.hh" 302665Ssaidi@eecs.umich.edu#include "kern/kernel_stats.hh" 312SN/A 322SN/Ausing namespace TheISA; 332SN/A 34363SN/Avoid 35363SN/ASkipFuncEvent::process(ExecContext *xc) 361354SN/A{ 372SN/A Addr newpc = xc->readIntReg(ReturnAddressReg); 382SN/A 392SN/A DPRINTF(PCEvent, "skipping %s: pc=%x, newpc=%x\n", description, 402SN/A xc->readPC(), newpc); 412SN/A 422SN/A xc->setPC(newpc); 43363SN/A xc->setNextPC(xc->readPC() + sizeof(TheISA::MachInst)); 4456SN/A 451388SN/A BranchPred *bp = xc->getCpuPtr()->getBranchPred(); 46217SN/A if (bp != NULL) { 47363SN/A bp->popRAS(xc->getThreadNum()); 4856SN/A } 4956SN/A} 5056SN/A 511638SN/A 5256SN/AFnEvent::FnEvent(PCEventQueue *q, const std::string &desc, Addr addr, 532SN/A Stats::MainBin *bin) 542356SN/A : PCEvent(q, desc, addr), _name(desc), mybin(bin) 552356SN/A{ 562356SN/A} 572SN/A 582SN/Avoid 594000Ssaidi@eecs.umich.eduFnEvent::process(ExecContext *xc) 604000Ssaidi@eecs.umich.edu{ 614762Snate@binkert.org if (xc->misspeculating()) 624762Snate@binkert.org return; 634762Snate@binkert.org 644762Snate@binkert.org xc->getSystemPtr()->kernelBinning->call(xc, mybin); 654762Snate@binkert.org} 664762Snate@binkert.org 674762Snate@binkert.orgvoid 684762Snate@binkert.orgIdleStartEvent::process(ExecContext *xc) 694762Snate@binkert.org{ 704762Snate@binkert.org xc->getCpuPtr()->kernelStats->setIdleProcess( 714762Snate@binkert.org xc->readMiscReg(AlphaISA::IPR_PALtemp23), xc); 724762Snate@binkert.org remove(); 734762Snate@binkert.org} 744762Snate@binkert.org 754762Snate@binkert.orgvoid 764762Snate@binkert.orgInterruptStartEvent::process(ExecContext *xc) 774762Snate@binkert.org{ 784762Snate@binkert.org xc->getCpuPtr()->kernelStats->mode(Kernel::interrupt, xc); 794762Snate@binkert.org} 804762Snate@binkert.org 814762Snate@binkert.orgvoid 824762Snate@binkert.orgInterruptEndEvent::process(ExecContext *xc) 834762Snate@binkert.org{ 844762Snate@binkert.org // We go back to kernel, if we are user, inside the rti 854762Snate@binkert.org // pal code we will get switched to user because of the ICM write 864762Snate@binkert.org xc->getCpuPtr()->kernelStats->mode(Kernel::kernel, xc); 874762Snate@binkert.org} 884762Snate@binkert.org