system_events.cc revision 1082
12SN/A/* 21762SN/A * Copyright (c) 2004 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282760Sbinkertn@umich.edu 292760Sbinkertn@umich.edu#include "cpu/exec_context.hh" 302665Ssaidi@eecs.umich.edu#include "cpu/base_cpu.hh" 312SN/A#include "cpu/full_cpu/bpred.hh" 322SN/A#include "cpu/full_cpu/full_cpu.hh" 332SN/A#include "kern/kernel_stats.hh" 34363SN/A#include "kern/system_events.hh" 35363SN/A#include "sim/system.hh" 361354SN/A 372SN/Avoid 382SN/ASkipFuncEvent::process(ExecContext *xc) 392SN/A{ 402SN/A Addr newpc = xc->regs.intRegFile[ReturnAddressReg]; 412SN/A 422SN/A DPRINTF(PCEvent, "skipping %s: pc=%x, newpc=%x\n", description, 434841Ssaidi@eecs.umich.edu xc->regs.pc, newpc); 44363SN/A 4556SN/A xc->regs.pc = newpc; 461388SN/A xc->regs.npc = xc->regs.pc + sizeof(MachInst); 47217SN/A 48363SN/A BranchPred *bp = xc->cpu->getBranchPred(); 4956SN/A if (bp != NULL) { 5056SN/A bp->popRAS(xc->thread_num); 5156SN/A } 521638SN/A} 5356SN/A 542SN/A 552356SN/AFnEvent::FnEvent(PCEventQueue *q, const std::string &desc, Stats::MainBin *bin) 562356SN/A : PCEvent(q, desc), _name(desc), mybin(bin) 572356SN/A{ 582SN/A} 592SN/A 604000Ssaidi@eecs.umich.eduvoid 614000Ssaidi@eecs.umich.eduFnEvent::process(ExecContext *xc) 624762Snate@binkert.org{ 634762Snate@binkert.org if (xc->misspeculating()) 644762Snate@binkert.org return; 654762Snate@binkert.org 664762Snate@binkert.org xc->system->kernelBinning->call(xc, mybin); 674762Snate@binkert.org} 684762Snate@binkert.org 694762Snate@binkert.orgvoid 704762Snate@binkert.orgIdleStartEvent::process(ExecContext *xc) 714762Snate@binkert.org{ 724762Snate@binkert.org xc->kernelStats->setIdleProcess(xc->regs.ipr[AlphaISA::IPR_PALtemp23]); 734762Snate@binkert.org} 744762Snate@binkert.org 754762Snate@binkert.orgvoid 764762Snate@binkert.orgInterruptStartEvent::process(ExecContext *xc) 774762Snate@binkert.org{ 784762Snate@binkert.org xc->kernelStats->mode(Kernel::interrupt); 794762Snate@binkert.org} 804762Snate@binkert.org 814762Snate@binkert.orgvoid 824762Snate@binkert.orgInterruptEndEvent::process(ExecContext *xc) 834762Snate@binkert.org{ 844762Snate@binkert.org // We go back to kernel, if we are user, inside the rti 854762Snate@binkert.org // pal code we will get switched to user because of the ICM write 864762Snate@binkert.org xc->kernelStats->mode(Kernel::kernel); 874762Snate@binkert.org} 884762Snate@binkert.org