system_events.cc revision 1070
12SN/A/*
21762SN/A * Copyright (c) 2004 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu */
282760Sbinkertn@umich.edu
292760Sbinkertn@umich.edu#include "cpu/exec_context.hh"
302665Ssaidi@eecs.umich.edu#include "cpu/base_cpu.hh"
312SN/A#include "cpu/full_cpu/bpred.hh"
322SN/A#include "cpu/full_cpu/full_cpu.hh"
338229Snate@binkert.org#include "kern/kernel_stats.hh"
342SN/A#include "kern/system_events.hh"
35363SN/A#include "sim/system.hh"
362SN/A
378229Snate@binkert.orgvoid
382SN/ASkipFuncEvent::process(ExecContext *xc)
392SN/A{
402SN/A    Addr newpc = xc->regs.intRegFile[ReturnAddressReg];
412SN/A
422SN/A    DPRINTF(PCEvent, "skipping %s: pc=%x, newpc=%x\n", description,
43363SN/A            xc->regs.pc, newpc);
4456SN/A
451388SN/A    xc->regs.pc = newpc;
46217SN/A    xc->regs.npc = xc->regs.pc + sizeof(MachInst);
47363SN/A
4856SN/A    BranchPred *bp = xc->cpu->getBranchPred();
4956SN/A    if (bp != NULL) {
5056SN/A        bp->popRAS(xc->thread_num);
511638SN/A    }
5256SN/A}
532SN/A
542356SN/A
552356SN/AFnEvent::FnEvent(PCEventQueue *q, const std::string &desc, Stats::MainBin *bin)
562356SN/A    : PCEvent(q, desc), _name(desc), mybin(bin)
572SN/A{
582SN/A}
594000Ssaidi@eecs.umich.edu
604000Ssaidi@eecs.umich.eduvoid
614762Snate@binkert.orgFnEvent::process(ExecContext *xc)
624762Snate@binkert.org{
634762Snate@binkert.org    if (xc->misspeculating())
644762Snate@binkert.org        return;
654762Snate@binkert.org
664762Snate@binkert.org    xc->system->kernelBinning->call(xc, mybin);
674762Snate@binkert.org}
684762Snate@binkert.org
694762Snate@binkert.orgvoid
704762Snate@binkert.orgIdleStartEvent::process(ExecContext *xc)
714762Snate@binkert.org{
724762Snate@binkert.org    xc->kernelStats->setIdleProcess(xc->regs.ipr[AlphaISA::IPR_PALtemp23]);
734762Snate@binkert.org}
744762Snate@binkert.org