1720SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3720SN/A * All rights reserved. 4720SN/A * 5720SN/A * Redistribution and use in source and binary forms, with or without 6720SN/A * modification, are permitted provided that the following conditions are 7720SN/A * met: redistributions of source code must retain the above copyright 8720SN/A * notice, this list of conditions and the following disclaimer; 9720SN/A * redistributions in binary form must reproduce the above copyright 10720SN/A * notice, this list of conditions and the following disclaimer in the 11720SN/A * documentation and/or other materials provided with the distribution; 12720SN/A * neither the name of the copyright holders nor the names of its 13720SN/A * contributors may be used to endorse or promote products derived from 14720SN/A * this software without specific prior written permission. 15720SN/A * 16720SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17720SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18720SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19720SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20720SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21720SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22720SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23720SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24720SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25720SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26720SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Lisa Hsu 292665Ssaidi@eecs.umich.edu * Nathan Binkert 30720SN/A */ 31720SN/A 3211793Sbrandon.potter@amd.com#include "kern/system_events.hh" 3311793Sbrandon.potter@amd.com 343566Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 357693SAli.Saidi@ARM.com#include "arch/utility.hh" 363549Sgblack@eecs.umich.edu#include "base/trace.hh" 376658Snate@binkert.org#include "config/the_isa.hh" 382683Sktlim@umich.edu#include "cpu/thread_context.hh" 398232Snate@binkert.org#include "debug/PCEvent.hh" 40720SN/A 412107SN/Ausing namespace TheISA; 422107SN/A 43720SN/Avoid 442680Sktlim@umich.eduSkipFuncEvent::process(ThreadContext *tc) 45720SN/A{ 467720Sgblack@eecs.umich.edu TheISA::PCState oldPC M5_VAR_USED = tc->pcState(); 47720SN/A 487693SAli.Saidi@ARM.com // Call ISA specific code to do the skipping 497693SAli.Saidi@ARM.com TheISA::skipFunction(tc); 507720Sgblack@eecs.umich.edu DPRINTF(PCEvent, "skipping %s: pc = %s, newpc = %s\n", description, 517720Sgblack@eecs.umich.edu oldPC, tc->pcState()); 52720SN/A} 53