wavefront.hh revision 11308
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 311308Santhony.gutierrez@amd.com * All rights reserved. 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * For use for simulation and test purposes only 611308Santhony.gutierrez@amd.com * 711308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 811308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are met: 911308Santhony.gutierrez@amd.com * 1011308Santhony.gutierrez@amd.com * 1. Redistributions of source code must retain the above copyright notice, 1111308Santhony.gutierrez@amd.com * this list of conditions and the following disclaimer. 1211308Santhony.gutierrez@amd.com * 1311308Santhony.gutierrez@amd.com * 2. Redistributions in binary form must reproduce the above copyright notice, 1411308Santhony.gutierrez@amd.com * this list of conditions and the following disclaimer in the documentation 1511308Santhony.gutierrez@amd.com * and/or other materials provided with the distribution. 1611308Santhony.gutierrez@amd.com * 1711308Santhony.gutierrez@amd.com * 3. Neither the name of the copyright holder nor the names of its contributors 1811308Santhony.gutierrez@amd.com * may be used to endorse or promote products derived from this software 1911308Santhony.gutierrez@amd.com * without specific prior written permission. 2011308Santhony.gutierrez@amd.com * 2111308Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2211308Santhony.gutierrez@amd.com * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2311308Santhony.gutierrez@amd.com * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2411308Santhony.gutierrez@amd.com * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2511308Santhony.gutierrez@amd.com * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2611308Santhony.gutierrez@amd.com * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2711308Santhony.gutierrez@amd.com * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2811308Santhony.gutierrez@amd.com * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2911308Santhony.gutierrez@amd.com * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3011308Santhony.gutierrez@amd.com * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3111308Santhony.gutierrez@amd.com * POSSIBILITY OF SUCH DAMAGE. 3211308Santhony.gutierrez@amd.com * 3311308Santhony.gutierrez@amd.com * Author: Lisa Hsu 3411308Santhony.gutierrez@amd.com */ 3511308Santhony.gutierrez@amd.com 3611308Santhony.gutierrez@amd.com#ifndef __WAVEFRONT_HH__ 3711308Santhony.gutierrez@amd.com#define __WAVEFRONT_HH__ 3811308Santhony.gutierrez@amd.com 3911308Santhony.gutierrez@amd.com#include <cassert> 4011308Santhony.gutierrez@amd.com#include <deque> 4111308Santhony.gutierrez@amd.com#include <memory> 4211308Santhony.gutierrez@amd.com#include <stack> 4311308Santhony.gutierrez@amd.com#include <vector> 4411308Santhony.gutierrez@amd.com 4511308Santhony.gutierrez@amd.com#include "base/misc.hh" 4611308Santhony.gutierrez@amd.com#include "base/types.hh" 4711308Santhony.gutierrez@amd.com#include "gpu-compute/condition_register_state.hh" 4811308Santhony.gutierrez@amd.com#include "gpu-compute/lds_state.hh" 4911308Santhony.gutierrez@amd.com#include "gpu-compute/misc.hh" 5011308Santhony.gutierrez@amd.com#include "params/Wavefront.hh" 5111308Santhony.gutierrez@amd.com#include "sim/sim_object.hh" 5211308Santhony.gutierrez@amd.com 5311308Santhony.gutierrez@amd.comstatic const int MAX_NUM_INSTS_PER_WF = 12; 5411308Santhony.gutierrez@amd.com 5511308Santhony.gutierrez@amd.com/* 5611308Santhony.gutierrez@amd.com * Arguments for the hsail opcode call, are user defined and variable length. 5711308Santhony.gutierrez@amd.com * The hardware/finalizer can support arguments in hardware or use memory to 5811308Santhony.gutierrez@amd.com * pass arguments. For now, let's assume that an unlimited number of arguments 5911308Santhony.gutierrez@amd.com * are supported in hardware (the compiler inlines functions whenver it can 6011308Santhony.gutierrez@amd.com * anyways, so unless someone is interested in the implications of linking/ 6111308Santhony.gutierrez@amd.com * library functions, I think this is a reasonable assumption given the typical 6211308Santhony.gutierrez@amd.com * size of an OpenCL kernel). 6311308Santhony.gutierrez@amd.com * 6411308Santhony.gutierrez@amd.com * Note that call args are different than kernel arguments: 6511308Santhony.gutierrez@amd.com * * All work-items in a kernel refer the same set of kernel arguments 6611308Santhony.gutierrez@amd.com * * Each work-item has it's on set of call args. So a call argument at 6711308Santhony.gutierrez@amd.com * address 0x4 is different for work-item 0 and work-item 1. 6811308Santhony.gutierrez@amd.com * 6911308Santhony.gutierrez@amd.com * Ok, the table below shows an example of how we organize the call arguments in 7011308Santhony.gutierrez@amd.com * the CallArgMem class. 7111308Santhony.gutierrez@amd.com * 7211308Santhony.gutierrez@amd.com * int foo(int arg1, double arg2) 7311308Santhony.gutierrez@amd.com * ___________________________________________________ 7411308Santhony.gutierrez@amd.com * | 0: return.0 | 4: return.1 | ... | 252: return.63 | 7511308Santhony.gutierrez@amd.com * |---------------------------------------------------| 7611308Santhony.gutierrez@amd.com * | 256: arg1.0 | 260: arg1.1 | ... | 508: arg1.63 | 7711308Santhony.gutierrez@amd.com * |---------------------------------------------------| 7811308Santhony.gutierrez@amd.com * | 512: arg2.0 | 520: arg2.1 | ... | 1016: arg2.63 | 7911308Santhony.gutierrez@amd.com * ___________________________________________________ 8011308Santhony.gutierrez@amd.com */ 8111308Santhony.gutierrez@amd.comclass CallArgMem 8211308Santhony.gutierrez@amd.com{ 8311308Santhony.gutierrez@amd.com public: 8411308Santhony.gutierrez@amd.com // pointer to buffer for storing function arguments 8511308Santhony.gutierrez@amd.com uint8_t *mem; 8611308Santhony.gutierrez@amd.com // size of function args 8711308Santhony.gutierrez@amd.com int funcArgsSizePerItem; 8811308Santhony.gutierrez@amd.com 8911308Santhony.gutierrez@amd.com template<typename CType> 9011308Santhony.gutierrez@amd.com int 9111308Santhony.gutierrez@amd.com getLaneOffset(int lane, int addr) 9211308Santhony.gutierrez@amd.com { 9311308Santhony.gutierrez@amd.com return addr * VSZ + sizeof(CType) * lane; 9411308Santhony.gutierrez@amd.com } 9511308Santhony.gutierrez@amd.com 9611308Santhony.gutierrez@amd.com CallArgMem(int func_args_size_per_item) 9711308Santhony.gutierrez@amd.com : funcArgsSizePerItem(func_args_size_per_item) 9811308Santhony.gutierrez@amd.com { 9911308Santhony.gutierrez@amd.com mem = (uint8_t*)malloc(funcArgsSizePerItem * VSZ); 10011308Santhony.gutierrez@amd.com } 10111308Santhony.gutierrez@amd.com 10211308Santhony.gutierrez@amd.com ~CallArgMem() 10311308Santhony.gutierrez@amd.com { 10411308Santhony.gutierrez@amd.com free(mem); 10511308Santhony.gutierrez@amd.com } 10611308Santhony.gutierrez@amd.com 10711308Santhony.gutierrez@amd.com template<typename CType> 10811308Santhony.gutierrez@amd.com uint8_t* 10911308Santhony.gutierrez@amd.com getLaneAddr(int lane, int addr) 11011308Santhony.gutierrez@amd.com { 11111308Santhony.gutierrez@amd.com return mem + getLaneOffset<CType>(lane, addr); 11211308Santhony.gutierrez@amd.com } 11311308Santhony.gutierrez@amd.com 11411308Santhony.gutierrez@amd.com template<typename CType> 11511308Santhony.gutierrez@amd.com void 11611308Santhony.gutierrez@amd.com setLaneAddr(int lane, int addr, CType val) 11711308Santhony.gutierrez@amd.com { 11811308Santhony.gutierrez@amd.com *((CType*)(mem + getLaneOffset<CType>(lane, addr))) = val; 11911308Santhony.gutierrez@amd.com } 12011308Santhony.gutierrez@amd.com}; 12111308Santhony.gutierrez@amd.com 12211308Santhony.gutierrez@amd.com/** 12311308Santhony.gutierrez@amd.com * A reconvergence stack entry conveys the necessary state to implement 12411308Santhony.gutierrez@amd.com * control flow divergence. 12511308Santhony.gutierrez@amd.com */ 12611308Santhony.gutierrez@amd.comclass ReconvergenceStackEntry { 12711308Santhony.gutierrez@amd.com 12811308Santhony.gutierrez@amd.com public: 12911308Santhony.gutierrez@amd.com ReconvergenceStackEntry(uint32_t new_pc, uint32_t new_rpc, 13011308Santhony.gutierrez@amd.com VectorMask new_mask) : pc(new_pc), rpc(new_rpc), 13111308Santhony.gutierrez@amd.com execMask(new_mask) { 13211308Santhony.gutierrez@amd.com } 13311308Santhony.gutierrez@amd.com 13411308Santhony.gutierrez@amd.com /** 13511308Santhony.gutierrez@amd.com * PC of current instruction. 13611308Santhony.gutierrez@amd.com */ 13711308Santhony.gutierrez@amd.com uint32_t pc; 13811308Santhony.gutierrez@amd.com /** 13911308Santhony.gutierrez@amd.com * PC of the immediate post-dominator instruction, i.e., the value of 14011308Santhony.gutierrez@amd.com * @a pc for the first instruction that will be executed by the wavefront 14111308Santhony.gutierrez@amd.com * when a reconvergence point is reached. 14211308Santhony.gutierrez@amd.com */ 14311308Santhony.gutierrez@amd.com uint32_t rpc; 14411308Santhony.gutierrez@amd.com /** 14511308Santhony.gutierrez@amd.com * Execution mask. 14611308Santhony.gutierrez@amd.com */ 14711308Santhony.gutierrez@amd.com VectorMask execMask; 14811308Santhony.gutierrez@amd.com}; 14911308Santhony.gutierrez@amd.com 15011308Santhony.gutierrez@amd.comclass Wavefront : public SimObject 15111308Santhony.gutierrez@amd.com{ 15211308Santhony.gutierrez@amd.com public: 15311308Santhony.gutierrez@amd.com enum itype_e {I_ALU,I_GLOBAL,I_SHARED,I_FLAT,I_PRIVATE}; 15411308Santhony.gutierrez@amd.com enum status_e {S_STOPPED,S_RETURNING,S_RUNNING}; 15511308Santhony.gutierrez@amd.com 15611308Santhony.gutierrez@amd.com // Base pointer for array of instruction pointers 15711308Santhony.gutierrez@amd.com uint64_t base_ptr; 15811308Santhony.gutierrez@amd.com 15911308Santhony.gutierrez@amd.com uint32_t old_barrier_cnt; 16011308Santhony.gutierrez@amd.com uint32_t barrier_cnt; 16111308Santhony.gutierrez@amd.com uint32_t barrier_id; 16211308Santhony.gutierrez@amd.com uint32_t barrier_slots; 16311308Santhony.gutierrez@amd.com status_e status; 16411308Santhony.gutierrez@amd.com // HW slot id where the WF is mapped to inside a SIMD unit 16511308Santhony.gutierrez@amd.com int wfSlotId; 16611308Santhony.gutierrez@amd.com int kern_id; 16711308Santhony.gutierrez@amd.com // SIMD unit where the WV has been scheduled 16811308Santhony.gutierrez@amd.com int simdId; 16911308Santhony.gutierrez@amd.com // pointer to parent CU 17011308Santhony.gutierrez@amd.com ComputeUnit *computeUnit; 17111308Santhony.gutierrez@amd.com 17211308Santhony.gutierrez@amd.com std::deque<GPUDynInstPtr> instructionBuffer; 17311308Santhony.gutierrez@amd.com 17411308Santhony.gutierrez@amd.com bool pendingFetch; 17511308Santhony.gutierrez@amd.com bool dropFetch; 17611308Santhony.gutierrez@amd.com 17711308Santhony.gutierrez@amd.com // Condition Register State (for HSAIL simulations only) 17811308Santhony.gutierrez@amd.com class ConditionRegisterState *condRegState; 17911308Santhony.gutierrez@amd.com // number of single precision VGPRs required by WF 18011308Santhony.gutierrez@amd.com uint32_t maxSpVgprs; 18111308Santhony.gutierrez@amd.com // number of double precision VGPRs required by WF 18211308Santhony.gutierrez@amd.com uint32_t maxDpVgprs; 18311308Santhony.gutierrez@amd.com // map virtual to physical vector register 18411308Santhony.gutierrez@amd.com uint32_t remap(uint32_t vgprIndex, uint32_t size, uint8_t mode=0); 18511308Santhony.gutierrez@amd.com void resizeRegFiles(int num_cregs, int num_sregs, int num_dregs); 18611308Santhony.gutierrez@amd.com bool isGmInstruction(GPUDynInstPtr ii); 18711308Santhony.gutierrez@amd.com bool isLmInstruction(GPUDynInstPtr ii); 18811308Santhony.gutierrez@amd.com bool isOldestInstGMem(); 18911308Santhony.gutierrez@amd.com bool isOldestInstLMem(); 19011308Santhony.gutierrez@amd.com bool isOldestInstPrivMem(); 19111308Santhony.gutierrez@amd.com bool isOldestInstFlatMem(); 19211308Santhony.gutierrez@amd.com bool isOldestInstALU(); 19311308Santhony.gutierrez@amd.com bool isOldestInstBarrier(); 19411308Santhony.gutierrez@amd.com // used for passing spill address to DDInstGPU 19511308Santhony.gutierrez@amd.com uint64_t last_addr[VSZ]; 19611308Santhony.gutierrez@amd.com uint32_t workitemid[3][VSZ]; 19711308Santhony.gutierrez@amd.com uint32_t workitemFlatId[VSZ]; 19811308Santhony.gutierrez@amd.com uint32_t workgroupid[3]; 19911308Santhony.gutierrez@amd.com uint32_t workgroupsz[3]; 20011308Santhony.gutierrez@amd.com uint32_t gridsz[3]; 20111308Santhony.gutierrez@amd.com uint32_t wg_id; 20211308Santhony.gutierrez@amd.com uint32_t wg_sz; 20311308Santhony.gutierrez@amd.com uint32_t dynwaveid; 20411308Santhony.gutierrez@amd.com uint32_t maxdynwaveid; 20511308Santhony.gutierrez@amd.com uint32_t dispatchid; 20611308Santhony.gutierrez@amd.com // outstanding global+local memory requests 20711308Santhony.gutierrez@amd.com uint32_t outstanding_reqs; 20811308Santhony.gutierrez@amd.com // memory requests between scoreboard 20911308Santhony.gutierrez@amd.com // and execute stage not yet executed 21011308Santhony.gutierrez@amd.com uint32_t mem_reqs_in_pipe; 21111308Santhony.gutierrez@amd.com // outstanding global memory write requests 21211308Santhony.gutierrez@amd.com uint32_t outstanding_reqs_wr_gm; 21311308Santhony.gutierrez@amd.com // outstanding local memory write requests 21411308Santhony.gutierrez@amd.com uint32_t outstanding_reqs_wr_lm; 21511308Santhony.gutierrez@amd.com // outstanding global memory read requests 21611308Santhony.gutierrez@amd.com uint32_t outstanding_reqs_rd_gm; 21711308Santhony.gutierrez@amd.com // outstanding local memory read requests 21811308Santhony.gutierrez@amd.com uint32_t outstanding_reqs_rd_lm; 21911308Santhony.gutierrez@amd.com uint32_t rd_lm_reqs_in_pipe; 22011308Santhony.gutierrez@amd.com uint32_t rd_gm_reqs_in_pipe; 22111308Santhony.gutierrez@amd.com uint32_t wr_lm_reqs_in_pipe; 22211308Santhony.gutierrez@amd.com uint32_t wr_gm_reqs_in_pipe; 22311308Santhony.gutierrez@amd.com 22411308Santhony.gutierrez@amd.com int mem_trace_busy; 22511308Santhony.gutierrez@amd.com uint64_t last_trace; 22611308Santhony.gutierrez@amd.com // number of vector registers reserved by WF 22711308Santhony.gutierrez@amd.com int reservedVectorRegs; 22811308Santhony.gutierrez@amd.com // Index into the Vector Register File's namespace where the WF's registers 22911308Santhony.gutierrez@amd.com // will live while the WF is executed 23011308Santhony.gutierrez@amd.com uint32_t startVgprIndex; 23111308Santhony.gutierrez@amd.com 23211308Santhony.gutierrez@amd.com // Old value of destination gpr (for trace) 23311308Santhony.gutierrez@amd.com uint32_t old_vgpr[VSZ]; 23411308Santhony.gutierrez@amd.com // Id of destination gpr (for trace) 23511308Santhony.gutierrez@amd.com uint32_t old_vgpr_id; 23611308Santhony.gutierrez@amd.com // Tick count of last old_vgpr copy 23711308Santhony.gutierrez@amd.com uint64_t old_vgpr_tcnt; 23811308Santhony.gutierrez@amd.com 23911308Santhony.gutierrez@amd.com // Old value of destination gpr (for trace) 24011308Santhony.gutierrez@amd.com uint64_t old_dgpr[VSZ]; 24111308Santhony.gutierrez@amd.com // Id of destination gpr (for trace) 24211308Santhony.gutierrez@amd.com uint32_t old_dgpr_id; 24311308Santhony.gutierrez@amd.com // Tick count of last old_vgpr copy 24411308Santhony.gutierrez@amd.com uint64_t old_dgpr_tcnt; 24511308Santhony.gutierrez@amd.com 24611308Santhony.gutierrez@amd.com // Execution mask at wavefront start 24711308Santhony.gutierrez@amd.com VectorMask init_mask; 24811308Santhony.gutierrez@amd.com 24911308Santhony.gutierrez@amd.com // number of barriers this WF has joined 25011308Santhony.gutierrez@amd.com int bar_cnt[VSZ]; 25111308Santhony.gutierrez@amd.com int max_bar_cnt; 25211308Santhony.gutierrez@amd.com // Flag to stall a wave on barrier 25311308Santhony.gutierrez@amd.com bool stalledAtBarrier; 25411308Santhony.gutierrez@amd.com 25511308Santhony.gutierrez@amd.com // a pointer to the fraction of the LDS allocated 25611308Santhony.gutierrez@amd.com // to this workgroup (thus this wavefront) 25711308Santhony.gutierrez@amd.com LdsChunk *ldsChunk; 25811308Santhony.gutierrez@amd.com 25911308Santhony.gutierrez@amd.com // A pointer to the spill area 26011308Santhony.gutierrez@amd.com Addr spillBase; 26111308Santhony.gutierrez@amd.com // The size of the spill area 26211308Santhony.gutierrez@amd.com uint32_t spillSizePerItem; 26311308Santhony.gutierrez@amd.com // The vector width of the spill area 26411308Santhony.gutierrez@amd.com uint32_t spillWidth; 26511308Santhony.gutierrez@amd.com 26611308Santhony.gutierrez@amd.com // A pointer to the private memory area 26711308Santhony.gutierrez@amd.com Addr privBase; 26811308Santhony.gutierrez@amd.com // The size of the private memory area 26911308Santhony.gutierrez@amd.com uint32_t privSizePerItem; 27011308Santhony.gutierrez@amd.com 27111308Santhony.gutierrez@amd.com // A pointer ot the read-only memory area 27211308Santhony.gutierrez@amd.com Addr roBase; 27311308Santhony.gutierrez@amd.com // size of the read-only memory area 27411308Santhony.gutierrez@amd.com uint32_t roSize; 27511308Santhony.gutierrez@amd.com 27611308Santhony.gutierrez@amd.com // pointer to buffer for storing kernel arguments 27711308Santhony.gutierrez@amd.com uint8_t *kernelArgs; 27811308Santhony.gutierrez@amd.com // unique WF id over all WFs executed across all CUs 27911308Santhony.gutierrez@amd.com uint64_t wfDynId; 28011308Santhony.gutierrez@amd.com 28111308Santhony.gutierrez@amd.com // number of times instruction issue for this wavefront is blocked 28211308Santhony.gutierrez@amd.com // due to VRF port availability 28311308Santhony.gutierrez@amd.com Stats::Scalar numTimesBlockedDueVrfPortAvail; 28411308Santhony.gutierrez@amd.com // number of times an instruction of a WF is blocked from being issued 28511308Santhony.gutierrez@amd.com // due to WAR and WAW dependencies 28611308Santhony.gutierrez@amd.com Stats::Scalar numTimesBlockedDueWAXDependencies; 28711308Santhony.gutierrez@amd.com // number of times an instruction of a WF is blocked from being issued 28811308Santhony.gutierrez@amd.com // due to WAR and WAW dependencies 28911308Santhony.gutierrez@amd.com Stats::Scalar numTimesBlockedDueRAWDependencies; 29011308Santhony.gutierrez@amd.com // distribution of executed instructions based on their register 29111308Santhony.gutierrez@amd.com // operands; this is used to highlight the load on the VRF 29211308Santhony.gutierrez@amd.com Stats::Distribution srcRegOpDist; 29311308Santhony.gutierrez@amd.com Stats::Distribution dstRegOpDist; 29411308Santhony.gutierrez@amd.com 29511308Santhony.gutierrez@amd.com // Functions to operate on call argument memory 29611308Santhony.gutierrez@amd.com // argument memory for hsail call instruction 29711308Santhony.gutierrez@amd.com CallArgMem *callArgMem; 29811308Santhony.gutierrez@amd.com void 29911308Santhony.gutierrez@amd.com initCallArgMem(int func_args_size_per_item) 30011308Santhony.gutierrez@amd.com { 30111308Santhony.gutierrez@amd.com callArgMem = new CallArgMem(func_args_size_per_item); 30211308Santhony.gutierrez@amd.com } 30311308Santhony.gutierrez@amd.com 30411308Santhony.gutierrez@amd.com template<typename CType> 30511308Santhony.gutierrez@amd.com CType 30611308Santhony.gutierrez@amd.com readCallArgMem(int lane, int addr) 30711308Santhony.gutierrez@amd.com { 30811308Santhony.gutierrez@amd.com return *((CType*)(callArgMem->getLaneAddr<CType>(lane, addr))); 30911308Santhony.gutierrez@amd.com } 31011308Santhony.gutierrez@amd.com 31111308Santhony.gutierrez@amd.com template<typename CType> 31211308Santhony.gutierrez@amd.com void 31311308Santhony.gutierrez@amd.com writeCallArgMem(int lane, int addr, CType val) 31411308Santhony.gutierrez@amd.com { 31511308Santhony.gutierrez@amd.com callArgMem->setLaneAddr<CType>(lane, addr, val); 31611308Santhony.gutierrez@amd.com } 31711308Santhony.gutierrez@amd.com 31811308Santhony.gutierrez@amd.com typedef WavefrontParams Params; 31911308Santhony.gutierrez@amd.com Wavefront(const Params *p); 32011308Santhony.gutierrez@amd.com ~Wavefront(); 32111308Santhony.gutierrez@amd.com virtual void init(); 32211308Santhony.gutierrez@amd.com 32311308Santhony.gutierrez@amd.com void 32411308Santhony.gutierrez@amd.com setParent(ComputeUnit *cu) 32511308Santhony.gutierrez@amd.com { 32611308Santhony.gutierrez@amd.com computeUnit = cu; 32711308Santhony.gutierrez@amd.com } 32811308Santhony.gutierrez@amd.com 32911308Santhony.gutierrez@amd.com void start(uint64_t _wfDynId, uint64_t _base_ptr); 33011308Santhony.gutierrez@amd.com 33111308Santhony.gutierrez@amd.com void exec(); 33211308Santhony.gutierrez@amd.com void updateResources(); 33311308Santhony.gutierrez@amd.com int ready(itype_e type); 33411308Santhony.gutierrez@amd.com bool instructionBufferHasBranch(); 33511308Santhony.gutierrez@amd.com void regStats(); 33611308Santhony.gutierrez@amd.com VectorMask get_pred() { return execMask() & init_mask; } 33711308Santhony.gutierrez@amd.com 33811308Santhony.gutierrez@amd.com bool waitingAtBarrier(int lane); 33911308Santhony.gutierrez@amd.com 34011308Santhony.gutierrez@amd.com void pushToReconvergenceStack(uint32_t pc, uint32_t rpc, 34111308Santhony.gutierrez@amd.com const VectorMask& exec_mask); 34211308Santhony.gutierrez@amd.com 34311308Santhony.gutierrez@amd.com void popFromReconvergenceStack(); 34411308Santhony.gutierrez@amd.com 34511308Santhony.gutierrez@amd.com uint32_t pc() const; 34611308Santhony.gutierrez@amd.com 34711308Santhony.gutierrez@amd.com uint32_t rpc() const; 34811308Santhony.gutierrez@amd.com 34911308Santhony.gutierrez@amd.com VectorMask execMask() const; 35011308Santhony.gutierrez@amd.com 35111308Santhony.gutierrez@amd.com bool execMask(int lane) const; 35211308Santhony.gutierrez@amd.com 35311308Santhony.gutierrez@amd.com void pc(uint32_t new_pc); 35411308Santhony.gutierrez@amd.com 35511308Santhony.gutierrez@amd.com void discardFetch(); 35611308Santhony.gutierrez@amd.com 35711308Santhony.gutierrez@amd.com private: 35811308Santhony.gutierrez@amd.com /** 35911308Santhony.gutierrez@amd.com * Stack containing Control Flow Graph nodes (i.e., kernel instructions) 36011308Santhony.gutierrez@amd.com * to be visited by the wavefront, and the associated execution masks. The 36111308Santhony.gutierrez@amd.com * reconvergence stack grows every time the wavefront reaches a divergence 36211308Santhony.gutierrez@amd.com * point (branch instruction), and shrinks every time the wavefront 36311308Santhony.gutierrez@amd.com * reaches a reconvergence point (immediate post-dominator instruction). 36411308Santhony.gutierrez@amd.com */ 36511308Santhony.gutierrez@amd.com std::stack<std::unique_ptr<ReconvergenceStackEntry>> reconvergenceStack; 36611308Santhony.gutierrez@amd.com}; 36711308Santhony.gutierrez@amd.com 36811308Santhony.gutierrez@amd.com#endif // __WAVEFRONT_HH__ 369