wavefront.cc revision 11640
12623SN/A/* 210596Sgabeblack@google.com * Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 312276Sanouk.vanlaer@arm.com * All rights reserved. 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * For use for simulation and test purposes only 67725SAli.Saidi@ARM.com * 77725SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 87725SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are met: 97725SAli.Saidi@ARM.com * 107725SAli.Saidi@ARM.com * 1. Redistributions of source code must retain the above copyright notice, 117725SAli.Saidi@ARM.com * this list of conditions and the following disclaimer. 127725SAli.Saidi@ARM.com * 137725SAli.Saidi@ARM.com * 2. Redistributions in binary form must reproduce the above copyright notice, 147725SAli.Saidi@ARM.com * this list of conditions and the following disclaimer in the documentation 152623SN/A * and/or other materials provided with the distribution. 162623SN/A * 172623SN/A * 3. Neither the name of the copyright holder nor the names of its contributors 182623SN/A * may be used to endorse or promote products derived from this software 192623SN/A * without specific prior written permission. 202623SN/A * 212623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 222623SN/A * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 232623SN/A * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 242623SN/A * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 252623SN/A * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 262623SN/A * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 272623SN/A * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 282623SN/A * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 292623SN/A * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 302623SN/A * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 312623SN/A * POSSIBILITY OF SUCH DAMAGE. 322623SN/A * 332623SN/A * Author: Lisa Hsu 342623SN/A */ 352623SN/A 362623SN/A#include "gpu-compute/wavefront.hh" 372623SN/A 382623SN/A#include "debug/GPUExec.hh" 392623SN/A#include "debug/WavefrontStack.hh" 402665Ssaidi@eecs.umich.edu#include "gpu-compute/code_enums.hh" 412665Ssaidi@eecs.umich.edu#include "gpu-compute/compute_unit.hh" 422623SN/A#include "gpu-compute/gpu_dyn_inst.hh" 432623SN/A#include "gpu-compute/shader.hh" 4411793Sbrandon.potter@amd.com#include "gpu-compute/vector_register_file.hh" 4511793Sbrandon.potter@amd.com 463170Sstever@eecs.umich.eduWavefront* 478105Sgblack@eecs.umich.eduWavefrontParams::create() 482623SN/A{ 494040Ssaidi@eecs.umich.edu return new Wavefront(this); 506658Snate@binkert.org} 512623SN/A 528232Snate@binkert.orgWavefront::Wavefront(const Params *p) 539152Satgutier@umich.edu : SimObject(p), callArgMem(nullptr) 548232Snate@binkert.org{ 5511793Sbrandon.potter@amd.com lastTrace = 0; 568232Snate@binkert.org simdId = p->simdId; 573348Sbinkertn@umich.edu wfSlotId = p->wf_slot_id; 583348Sbinkertn@umich.edu status = S_STOPPED; 594762Snate@binkert.org reservedVectorRegs = 0; 607678Sgblack@eecs.umich.edu startVgprIndex = 0; 618779Sgblack@eecs.umich.edu outstandingReqs = 0; 622901Ssaidi@eecs.umich.edu memReqsInPipe = 0; 632623SN/A outstandingReqsWrGm = 0; 642623SN/A outstandingReqsWrLm = 0; 652623SN/A outstandingReqsRdGm = 0; 662623SN/A outstandingReqsRdLm = 0; 672623SN/A rdLmReqsInPipe = 0; 682623SN/A rdGmReqsInPipe = 0; 692623SN/A wrLmReqsInPipe = 0; 7011147Smitch.hayenga@arm.com wrGmReqsInPipe = 0; 712623SN/A 722623SN/A barrierCnt = 0; 732623SN/A oldBarrierCnt = 0; 748707Sandreas.hansson@arm.com stalledAtBarrier = false; 752948Ssaidi@eecs.umich.edu 762948Ssaidi@eecs.umich.edu memTraceBusy = 0; 775606Snate@binkert.org oldVgprTcnt = 0xffffffffffffffffll; 782948Ssaidi@eecs.umich.edu oldDgprTcnt = 0xffffffffffffffffll; 792948Ssaidi@eecs.umich.edu oldVgpr.resize(p->wfSize); 805529Snate@binkert.org 818707Sandreas.hansson@arm.com pendingFetch = false; 829179Sandreas.hansson@arm.com dropFetch = false; 8312085Sspwilson2@wisc.edu condRegState = new ConditionRegisterState(); 842623SN/A maxSpVgprs = 0; 852623SN/A maxDpVgprs = 0; 862623SN/A lastAddr.resize(p->wfSize); 872623SN/A workItemFlatId.resize(p->wfSize); 882623SN/A oldDgpr.resize(p->wfSize); 8910030SAli.Saidi@ARM.com barCnt.resize(p->wfSize); 902623SN/A for (int i = 0; i < 3; ++i) { 912623SN/A workItemId[i].resize(p->wfSize); 922623SN/A } 932623SN/A} 9410913Sandreas.sandberg@arm.com 9510913Sandreas.sandberg@arm.comvoid 962798Sktlim@umich.eduWavefront::regStats() 9712276Sanouk.vanlaer@arm.com{ 9812276Sanouk.vanlaer@arm.com SimObject::regStats(); 9912276Sanouk.vanlaer@arm.com 1009448SAndreas.Sandberg@ARM.com srcRegOpDist 10110913Sandreas.sandberg@arm.com .init(0, 4, 2) 1029448SAndreas.Sandberg@ARM.com .name(name() + ".src_reg_operand_dist") 1039342SAndreas.Sandberg@arm.com .desc("number of executed instructions with N source register operands") 1049448SAndreas.Sandberg@ARM.com ; 1059442SAndreas.Sandberg@ARM.com 10611147Smitch.hayenga@arm.com dstRegOpDist 10710913Sandreas.sandberg@arm.com .init(0, 3, 2) 1082798Sktlim@umich.edu .name(name() + ".dst_reg_operand_dist") 10911147Smitch.hayenga@arm.com .desc("number of executed instructions with N destination register " 1109442SAndreas.Sandberg@ARM.com "operands") 1119442SAndreas.Sandberg@ARM.com ; 1129442SAndreas.Sandberg@ARM.com 1139442SAndreas.Sandberg@ARM.com // FIXME: the name of the WF needs to be unique 1149448SAndreas.Sandberg@ARM.com numTimesBlockedDueWAXDependencies 1159648Sdam.sunwoo@arm.com .name(name() + ".timesBlockedDueWAXDependencies") 1169442SAndreas.Sandberg@ARM.com .desc("number of times the wf's instructions are blocked due to WAW " 11710913Sandreas.sandberg@arm.com "or WAR dependencies") 1182798Sktlim@umich.edu ; 1192623SN/A 1202623SN/A // FIXME: the name of the WF needs to be unique 1212623SN/A numTimesBlockedDueRAWDependencies 1229342SAndreas.Sandberg@arm.com .name(name() + ".timesBlockedDueRAWDependencies") 1232623SN/A .desc("number of times the wf's instructions are blocked due to RAW " 1249442SAndreas.Sandberg@ARM.com "dependencies") 1259448SAndreas.Sandberg@ARM.com ; 1269448SAndreas.Sandberg@ARM.com 1279442SAndreas.Sandberg@ARM.com // FIXME: the name of the WF needs to be unique 1285221Ssaidi@eecs.umich.edu numTimesBlockedDueVrfPortAvail 1299523SAndreas.Sandberg@ARM.com .name(name() + ".timesBlockedDueVrfPortAvail") 1303201Shsul@eecs.umich.edu .desc("number of times instructions are blocked due to VRF port " 1319448SAndreas.Sandberg@ARM.com "availability") 1329448SAndreas.Sandberg@ARM.com ; 13311147Smitch.hayenga@arm.com} 13411147Smitch.hayenga@arm.com 13511147Smitch.hayenga@arm.comvoid 13611147Smitch.hayenga@arm.comWavefront::init() 13711147Smitch.hayenga@arm.com{ 13811147Smitch.hayenga@arm.com reservedVectorRegs = 0; 13911147Smitch.hayenga@arm.com startVgprIndex = 0; 14011147Smitch.hayenga@arm.com} 14111147Smitch.hayenga@arm.com 14211147Smitch.hayenga@arm.comvoid 14311147Smitch.hayenga@arm.comWavefront::resizeRegFiles(int num_cregs, int num_sregs, int num_dregs) 14411147Smitch.hayenga@arm.com{ 14511147Smitch.hayenga@arm.com condRegState->init(num_cregs); 14611147Smitch.hayenga@arm.com maxSpVgprs = num_sregs; 14711147Smitch.hayenga@arm.com maxDpVgprs = num_dregs; 14811147Smitch.hayenga@arm.com} 14911147Smitch.hayenga@arm.com 1502623SN/AWavefront::~Wavefront() 15111147Smitch.hayenga@arm.com{ 15212276Sanouk.vanlaer@arm.com if (callArgMem) 15312276Sanouk.vanlaer@arm.com delete callArgMem; 15412276Sanouk.vanlaer@arm.com delete condRegState; 15511147Smitch.hayenga@arm.com} 1569442SAndreas.Sandberg@ARM.com 1572798Sktlim@umich.eduvoid 1589442SAndreas.Sandberg@ARM.comWavefront::start(uint64_t _wf_dyn_id,uint64_t _base_ptr) 1599442SAndreas.Sandberg@ARM.com{ 1609442SAndreas.Sandberg@ARM.com wfDynId = _wf_dyn_id; 16110913Sandreas.sandberg@arm.com basePtr = _base_ptr; 1629442SAndreas.Sandberg@ARM.com status = S_RUNNING; 1639442SAndreas.Sandberg@ARM.com} 16411147Smitch.hayenga@arm.com 1659442SAndreas.Sandberg@ARM.combool 1669442SAndreas.Sandberg@ARM.comWavefront::isGmInstruction(GPUDynInstPtr ii) 1679442SAndreas.Sandberg@ARM.com{ 1689442SAndreas.Sandberg@ARM.com if (IS_OT_READ_PM(ii->opType()) || IS_OT_WRITE_PM(ii->opType()) || 16910913Sandreas.sandberg@arm.com IS_OT_ATOMIC_PM(ii->opType())) { 1709442SAndreas.Sandberg@ARM.com return true; 1719442SAndreas.Sandberg@ARM.com } 1722798Sktlim@umich.edu 1732798Sktlim@umich.edu if (IS_OT_READ_GM(ii->opType()) || IS_OT_WRITE_GM(ii->opType()) || 1742798Sktlim@umich.edu IS_OT_ATOMIC_GM(ii->opType())) { 1752798Sktlim@umich.edu return true; 1762798Sktlim@umich.edu } 17711147Smitch.hayenga@arm.com 17811147Smitch.hayenga@arm.com if (IS_OT_FLAT(ii->opType())) { 17911147Smitch.hayenga@arm.com return true; 1809429SAndreas.Sandberg@ARM.com } 1819429SAndreas.Sandberg@ARM.com 1829442SAndreas.Sandberg@ARM.com return false; 1839342SAndreas.Sandberg@arm.com} 18411147Smitch.hayenga@arm.com 18511147Smitch.hayenga@arm.combool 1869442SAndreas.Sandberg@ARM.comWavefront::isLmInstruction(GPUDynInstPtr ii) 18710464SAndreas.Sandberg@ARM.com{ 18812284Sjose.marinho@arm.com if (IS_OT_READ_LM(ii->opType()) || IS_OT_WRITE_LM(ii->opType()) || 1892623SN/A IS_OT_ATOMIC_LM(ii->opType())) { 1902623SN/A return true; 1912623SN/A } 1922623SN/A 1932623SN/A return false; 1942623SN/A} 1959429SAndreas.Sandberg@ARM.com 1962623SN/Abool 1979179Sandreas.hansson@arm.comWavefront::isOldestInstALU() 1982623SN/A{ 1992623SN/A assert(!instructionBuffer.empty()); 2009523SAndreas.Sandberg@ARM.com GPUDynInstPtr ii = instructionBuffer.front(); 2019523SAndreas.Sandberg@ARM.com 2029523SAndreas.Sandberg@ARM.com if (status != S_STOPPED && (ii->opType() == Enums::OT_NOP || 2039524SAndreas.Sandberg@ARM.com ii->opType() == Enums::OT_RET || ii->opType() == Enums::OT_BRANCH || 2049523SAndreas.Sandberg@ARM.com ii->opType() == Enums::OT_ALU || IS_OT_LDAS(ii->opType()) || 2059523SAndreas.Sandberg@ARM.com ii->opType() == Enums::OT_KERN_READ)) { 2069523SAndreas.Sandberg@ARM.com return true; 2079523SAndreas.Sandberg@ARM.com } 2082623SN/A 2092623SN/A return false; 21010407Smitch.hayenga@arm.com} 2112623SN/A 21210407Smitch.hayenga@arm.combool 2135221Ssaidi@eecs.umich.eduWavefront::isOldestInstBarrier() 21411147Smitch.hayenga@arm.com{ 2152623SN/A assert(!instructionBuffer.empty()); 21611147Smitch.hayenga@arm.com GPUDynInstPtr ii = instructionBuffer.front(); 21711147Smitch.hayenga@arm.com 21811147Smitch.hayenga@arm.com if (status != S_STOPPED && ii->opType() == Enums::OT_BARRIER) { 2193686Sktlim@umich.edu return true; 2202623SN/A } 22111147Smitch.hayenga@arm.com 22211147Smitch.hayenga@arm.com return false; 22311147Smitch.hayenga@arm.com} 22411147Smitch.hayenga@arm.com 22511147Smitch.hayenga@arm.combool 22611147Smitch.hayenga@arm.comWavefront::isOldestInstGMem() 22711147Smitch.hayenga@arm.com{ 22811526Sdavid.guillen@arm.com assert(!instructionBuffer.empty()); 22911526Sdavid.guillen@arm.com GPUDynInstPtr ii = instructionBuffer.front(); 2302623SN/A 2312623SN/A if (status != S_STOPPED && (IS_OT_READ_GM(ii->opType()) || 2322623SN/A IS_OT_WRITE_GM(ii->opType()) || IS_OT_ATOMIC_GM(ii->opType()))) { 2332623SN/A 2348737Skoansin.tan@gmail.com return true; 2352623SN/A } 2365221Ssaidi@eecs.umich.edu 2375221Ssaidi@eecs.umich.edu return false; 23811147Smitch.hayenga@arm.com} 23911147Smitch.hayenga@arm.com 2402623SN/Abool 2416043Sgblack@eecs.umich.eduWavefront::isOldestInstLMem() 2426043Sgblack@eecs.umich.edu{ 2436043Sgblack@eecs.umich.edu assert(!instructionBuffer.empty()); 2449342SAndreas.Sandberg@arm.com GPUDynInstPtr ii = instructionBuffer.front(); 2452623SN/A 24611147Smitch.hayenga@arm.com if (status != S_STOPPED && (IS_OT_READ_LM(ii->opType()) || 2472623SN/A IS_OT_WRITE_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType()))) { 24811147Smitch.hayenga@arm.com 24911147Smitch.hayenga@arm.com return true; 25011147Smitch.hayenga@arm.com } 25111147Smitch.hayenga@arm.com 25211147Smitch.hayenga@arm.com return false; 25311147Smitch.hayenga@arm.com} 25411147Smitch.hayenga@arm.com 25511526Sdavid.guillen@arm.combool 25611526Sdavid.guillen@arm.comWavefront::isOldestInstPrivMem() 2572623SN/A{ 2582623SN/A assert(!instructionBuffer.empty()); 2595728Sgblack@eecs.umich.edu GPUDynInstPtr ii = instructionBuffer.front(); 2605728Sgblack@eecs.umich.edu 2615728Sgblack@eecs.umich.edu if (status != S_STOPPED && (IS_OT_READ_PM(ii->opType()) || 26211147Smitch.hayenga@arm.com IS_OT_WRITE_PM(ii->opType()) || IS_OT_ATOMIC_PM(ii->opType()))) { 26311147Smitch.hayenga@arm.com 26411147Smitch.hayenga@arm.com return true; 2655728Sgblack@eecs.umich.edu } 26610533Sali.saidi@arm.com 26710533Sali.saidi@arm.com return false; 26810533Sali.saidi@arm.com} 26910533Sali.saidi@arm.com 27010533Sali.saidi@arm.combool 27110533Sali.saidi@arm.comWavefront::isOldestInstFlatMem() 2728105Sgblack@eecs.umich.edu{ 2739180Sandreas.hansson@arm.com assert(!instructionBuffer.empty()); 2749179Sandreas.hansson@arm.com GPUDynInstPtr ii = instructionBuffer.front(); 2755728Sgblack@eecs.umich.edu 2765728Sgblack@eecs.umich.edu if (status != S_STOPPED && IS_OT_FLAT(ii->opType())) { 2778975Sandreas.hansson@arm.com 2785728Sgblack@eecs.umich.edu return true; 2795728Sgblack@eecs.umich.edu } 2805728Sgblack@eecs.umich.edu 2815728Sgblack@eecs.umich.edu return false; 2825728Sgblack@eecs.umich.edu} 2835728Sgblack@eecs.umich.edu 2845728Sgblack@eecs.umich.edu// Return true if the Wavefront's instruction 2855728Sgblack@eecs.umich.edu// buffer has branch instruction. 2865728Sgblack@eecs.umich.edubool 2872623SN/AWavefront::instructionBufferHasBranch() 2885894Sgblack@eecs.umich.edu{ 2896973Stjones1@inf.ed.ac.uk for (auto it : instructionBuffer) { 2906973Stjones1@inf.ed.ac.uk GPUDynInstPtr ii = it; 2915744Sgblack@eecs.umich.edu 29211147Smitch.hayenga@arm.com if (ii->opType() == Enums::OT_RET || ii->opType() == Enums::OT_BRANCH) { 29311147Smitch.hayenga@arm.com return true; 29411147Smitch.hayenga@arm.com } 29510653Sandreas.hansson@arm.com } 29610566Sandreas.hansson@arm.com 2975894Sgblack@eecs.umich.edu return false; 2985894Sgblack@eecs.umich.edu} 2995894Sgblack@eecs.umich.edu 3005894Sgblack@eecs.umich.edu// Remap HSAIL register to physical VGPR. 3015894Sgblack@eecs.umich.edu// HSAIL register = virtual register assigned to an operand by HLC compiler 3025894Sgblack@eecs.umich.eduuint32_t 3035894Sgblack@eecs.umich.eduWavefront::remap(uint32_t vgprIndex, uint32_t size, uint8_t mode) 3045894Sgblack@eecs.umich.edu{ 3055894Sgblack@eecs.umich.edu assert((vgprIndex < reservedVectorRegs) && (reservedVectorRegs > 0)); 3066102Sgblack@eecs.umich.edu // add the offset from where the VGPRs of the wavefront have been assigned 30710030SAli.Saidi@ARM.com uint32_t physicalVgprIndex = startVgprIndex + vgprIndex; 3085894Sgblack@eecs.umich.edu // HSAIL double precision (DP) register: calculate the physical VGPR index 3095894Sgblack@eecs.umich.edu // assuming that DP registers are placed after SP ones in the VRF. The DP 3105894Sgblack@eecs.umich.edu // and SP VGPR name spaces in HSAIL mode are separate so we need to adjust 3115894Sgblack@eecs.umich.edu // the DP VGPR index before mapping it to the physical VRF address space 3125894Sgblack@eecs.umich.edu if (mode == 1 && size > 4) { 3135894Sgblack@eecs.umich.edu physicalVgprIndex = startVgprIndex + maxSpVgprs + (2 * vgprIndex); 3145894Sgblack@eecs.umich.edu } 3155894Sgblack@eecs.umich.edu 31611148Smitch.hayenga@arm.com assert((startVgprIndex <= physicalVgprIndex) && 3175894Sgblack@eecs.umich.edu (startVgprIndex + reservedVectorRegs - 1) >= physicalVgprIndex); 3185894Sgblack@eecs.umich.edu 3195894Sgblack@eecs.umich.edu // calculate absolute physical VGPR index 3205894Sgblack@eecs.umich.edu return physicalVgprIndex % computeUnit->vrf[simdId]->numRegs(); 3215894Sgblack@eecs.umich.edu} 3225894Sgblack@eecs.umich.edu 3235894Sgblack@eecs.umich.edu// Return true if this wavefront is ready 3245894Sgblack@eecs.umich.edu// to execute an instruction of the specified type. 3256973Stjones1@inf.ed.ac.ukint 3266973Stjones1@inf.ed.ac.ukWavefront::ready(itype_e type) 3275894Sgblack@eecs.umich.edu{ 3285894Sgblack@eecs.umich.edu // Check to make sure wave is running 3295894Sgblack@eecs.umich.edu if (status == S_STOPPED || status == S_RETURNING || 3305894Sgblack@eecs.umich.edu instructionBuffer.empty()) { 3315894Sgblack@eecs.umich.edu return 0; 3325894Sgblack@eecs.umich.edu } 3335894Sgblack@eecs.umich.edu 3345894Sgblack@eecs.umich.edu // Is the wave waiting at a barrier 3357911Shestness@cs.utexas.edu if (stalledAtBarrier) { 3367911Shestness@cs.utexas.edu if (!computeUnit->AllAtBarrier(barrierId,barrierCnt, 3375894Sgblack@eecs.umich.edu computeUnit->getRefCounter(dispatchId, wgId))) { 3385894Sgblack@eecs.umich.edu // Are all threads at barrier? 3397911Shestness@cs.utexas.edu return 0; 3407911Shestness@cs.utexas.edu } 3415894Sgblack@eecs.umich.edu oldBarrierCnt = barrierCnt; 3425894Sgblack@eecs.umich.edu stalledAtBarrier = false; 3435894Sgblack@eecs.umich.edu } 3445894Sgblack@eecs.umich.edu 3455894Sgblack@eecs.umich.edu // Read instruction 3465894Sgblack@eecs.umich.edu GPUDynInstPtr ii = instructionBuffer.front(); 3477911Shestness@cs.utexas.edu 3487911Shestness@cs.utexas.edu bool ready_inst M5_VAR_USED = false; 3495894Sgblack@eecs.umich.edu bool glbMemBusRdy = false; 3505894Sgblack@eecs.umich.edu bool glbMemIssueRdy = false; 3515894Sgblack@eecs.umich.edu if (type == I_GLOBAL || type == I_FLAT || type == I_PRIVATE) { 3527911Shestness@cs.utexas.edu for (int j=0; j < computeUnit->numGlbMemUnits; ++j) { 3537911Shestness@cs.utexas.edu if (computeUnit->vrfToGlobalMemPipeBus[j].prerdy()) 3545894Sgblack@eecs.umich.edu glbMemBusRdy = true; 3555894Sgblack@eecs.umich.edu if (computeUnit->wfWait[j].prerdy()) 3565894Sgblack@eecs.umich.edu glbMemIssueRdy = true; 3575894Sgblack@eecs.umich.edu } 3585894Sgblack@eecs.umich.edu } 3595894Sgblack@eecs.umich.edu bool locMemBusRdy = false; 3605894Sgblack@eecs.umich.edu bool locMemIssueRdy = false; 3615894Sgblack@eecs.umich.edu if (type == I_SHARED || type == I_FLAT) { 36210379Sandreas.hansson@arm.com for (int j=0; j < computeUnit->numLocMemUnits; ++j) { 3635894Sgblack@eecs.umich.edu if (computeUnit->vrfToLocalMemPipeBus[j].prerdy()) 3646739Sgblack@eecs.umich.edu locMemBusRdy = true; 3656739Sgblack@eecs.umich.edu if (computeUnit->wfWait[j].prerdy()) 36610464SAndreas.Sandberg@ARM.com locMemIssueRdy = true; 36712284Sjose.marinho@arm.com } 3685894Sgblack@eecs.umich.edu } 3695894Sgblack@eecs.umich.edu 3705894Sgblack@eecs.umich.edu // The following code is very error prone and the entire process for 3715894Sgblack@eecs.umich.edu // checking readiness will be fixed eventually. In the meantime, let's 3725894Sgblack@eecs.umich.edu // make sure that we do not silently let an instruction type slip 3735744Sgblack@eecs.umich.edu // through this logic and always return not ready. 3745744Sgblack@eecs.umich.edu if (!(ii->opType() == Enums::OT_BARRIER || ii->opType() == Enums::OT_NOP || 3755894Sgblack@eecs.umich.edu ii->opType() == Enums::OT_RET || ii->opType() == Enums::OT_BRANCH || 3765894Sgblack@eecs.umich.edu ii->opType() == Enums::OT_ALU || IS_OT_LDAS(ii->opType()) || 3779442SAndreas.Sandberg@ARM.com ii->opType() == Enums::OT_KERN_READ || 3785894Sgblack@eecs.umich.edu ii->opType() == Enums::OT_ARG || 3795894Sgblack@eecs.umich.edu IS_OT_READ_GM(ii->opType()) || IS_OT_WRITE_GM(ii->opType()) || 38010653Sandreas.hansson@arm.com IS_OT_ATOMIC_GM(ii->opType()) || IS_OT_READ_LM(ii->opType()) || 38110653Sandreas.hansson@arm.com IS_OT_WRITE_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType()) || 3825894Sgblack@eecs.umich.edu IS_OT_READ_PM(ii->opType()) || IS_OT_WRITE_PM(ii->opType()) || 38310653Sandreas.hansson@arm.com IS_OT_ATOMIC_PM(ii->opType()) || IS_OT_FLAT(ii->opType()))) { 3845894Sgblack@eecs.umich.edu panic("next instruction: %s is of unknown type\n", ii->disassemble()); 3855894Sgblack@eecs.umich.edu } 3865894Sgblack@eecs.umich.edu 3875894Sgblack@eecs.umich.edu DPRINTF(GPUExec, "CU%d: WF[%d][%d]: Checking Read for Inst : %s\n", 3885894Sgblack@eecs.umich.edu computeUnit->cu_id, simdId, wfSlotId, ii->disassemble()); 3895894Sgblack@eecs.umich.edu 3905894Sgblack@eecs.umich.edu if (type == I_ALU && ii->opType() == Enums::OT_BARRIER) { 3915894Sgblack@eecs.umich.edu // Here for ALU instruction (barrier) 3925894Sgblack@eecs.umich.edu if (!computeUnit->wfWait[simdId].prerdy()) { 3938105Sgblack@eecs.umich.edu // Is wave slot free? 3945744Sgblack@eecs.umich.edu return 0; 3955894Sgblack@eecs.umich.edu } 39610653Sandreas.hansson@arm.com 3975894Sgblack@eecs.umich.edu // Are there in pipe or outstanding memory requests? 3985894Sgblack@eecs.umich.edu if ((outstandingReqs + memReqsInPipe) > 0) { 3995894Sgblack@eecs.umich.edu return 0; 40010653Sandreas.hansson@arm.com } 40110653Sandreas.hansson@arm.com 4025894Sgblack@eecs.umich.edu ready_inst = true; 4038949Sandreas.hansson@arm.com } else if (type == I_ALU && ii->opType() == Enums::OT_NOP) { 4045744Sgblack@eecs.umich.edu // Here for ALU instruction (nop) 40510566Sandreas.hansson@arm.com if (!computeUnit->wfWait[simdId].prerdy()) { 4065744Sgblack@eecs.umich.edu // Is wave slot free? 4075744Sgblack@eecs.umich.edu return 0; 4085744Sgblack@eecs.umich.edu } 4095744Sgblack@eecs.umich.edu 4105744Sgblack@eecs.umich.edu ready_inst = true; 4115744Sgblack@eecs.umich.edu } else if (type == I_ALU && ii->opType() == Enums::OT_RET) { 4125744Sgblack@eecs.umich.edu // Here for ALU instruction (return) 4135744Sgblack@eecs.umich.edu if (!computeUnit->wfWait[simdId].prerdy()) { 4145744Sgblack@eecs.umich.edu // Is wave slot free? 4155744Sgblack@eecs.umich.edu return 0; 4165744Sgblack@eecs.umich.edu } 4175744Sgblack@eecs.umich.edu 4182623SN/A // Are there in pipe or outstanding memory requests? 4198444Sgblack@eecs.umich.edu if ((outstandingReqs + memReqsInPipe) > 0) { 42011608Snikos.nikoleris@arm.com return 0; 4212623SN/A } 42211303Ssteve.reinhardt@amd.com 42311303Ssteve.reinhardt@amd.com ready_inst = true; 42411303Ssteve.reinhardt@amd.com } else if (type == I_ALU && (ii->opType() == Enums::OT_BRANCH || 42511303Ssteve.reinhardt@amd.com ii->opType() == Enums::OT_ALU || IS_OT_LDAS(ii->opType()) || 42611303Ssteve.reinhardt@amd.com ii->opType() == Enums::OT_KERN_READ || 42711608Snikos.nikoleris@arm.com ii->opType() == Enums::OT_ARG)) { 42811608Snikos.nikoleris@arm.com // Here for ALU instruction (all others) 42911303Ssteve.reinhardt@amd.com if (!computeUnit->wfWait[simdId].prerdy()) { 43011147Smitch.hayenga@arm.com // Is alu slot free? 43111147Smitch.hayenga@arm.com return 0; 43211147Smitch.hayenga@arm.com } 4335728Sgblack@eecs.umich.edu if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii, 4345728Sgblack@eecs.umich.edu VrfAccessType::RD_WR)) { 4357720Sgblack@eecs.umich.edu return 0; 4369814Sandreas.hansson@arm.com } 4376973Stjones1@inf.ed.ac.uk 4382623SN/A if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) { 43910665SAli.Saidi@ARM.com return 0; 44010665SAli.Saidi@ARM.com } 4417045Ssteve.reinhardt@amd.com ready_inst = true; 44211435Smitch.hayenga@arm.com } else if (type == I_GLOBAL && (IS_OT_READ_GM(ii->opType()) || 44311435Smitch.hayenga@arm.com IS_OT_WRITE_GM(ii->opType()) || IS_OT_ATOMIC_GM(ii->opType()))) { 4445728Sgblack@eecs.umich.edu // Here Global memory instruction 44510024Sdam.sunwoo@arm.com if (IS_OT_READ_GM(ii->opType()) || IS_OT_ATOMIC_GM(ii->opType())) { 44610024Sdam.sunwoo@arm.com // Are there in pipe or outstanding global memory write requests? 4477520Sgblack@eecs.umich.edu if ((outstandingReqsWrGm + wrGmReqsInPipe) > 0) { 4485744Sgblack@eecs.umich.edu return 0; 4495728Sgblack@eecs.umich.edu } 4505894Sgblack@eecs.umich.edu } 4515744Sgblack@eecs.umich.edu 4525894Sgblack@eecs.umich.edu if (IS_OT_WRITE_GM(ii->opType()) || IS_OT_ATOMIC_GM(ii->opType()) || 4536102Sgblack@eecs.umich.edu IS_OT_HIST_GM(ii->opType())) { 4545894Sgblack@eecs.umich.edu // Are there in pipe or outstanding global memory read requests? 4555894Sgblack@eecs.umich.edu if ((outstandingReqsRdGm + rdGmReqsInPipe) > 0) 4566973Stjones1@inf.ed.ac.uk return 0; 4577520Sgblack@eecs.umich.edu } 4586973Stjones1@inf.ed.ac.uk 4598486Sgblack@eecs.umich.edu if (!glbMemIssueRdy) { 4608486Sgblack@eecs.umich.edu // Is WV issue slot free? 4618486Sgblack@eecs.umich.edu return 0; 4628486Sgblack@eecs.umich.edu } 4636973Stjones1@inf.ed.ac.uk 46411147Smitch.hayenga@arm.com if (!glbMemBusRdy) { 46511147Smitch.hayenga@arm.com // Is there an available VRF->Global memory read bus? 4665744Sgblack@eecs.umich.edu return 0; 4676973Stjones1@inf.ed.ac.uk } 4687520Sgblack@eecs.umich.edu 4698486Sgblack@eecs.umich.edu if (!computeUnit->globalMemoryPipe. 4708486Sgblack@eecs.umich.edu isGMReqFIFOWrRdy(rdGmReqsInPipe + wrGmReqsInPipe)) { 47111147Smitch.hayenga@arm.com // Can we insert a new request to the Global Mem Request FIFO? 4722623SN/A return 0; 4732623SN/A } 4745728Sgblack@eecs.umich.edu // can we schedule source & destination operands on the VRF? 4752623SN/A if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii, 4762623SN/A VrfAccessType::RD_WR)) { 4775728Sgblack@eecs.umich.edu return 0; 4785728Sgblack@eecs.umich.edu } 4795728Sgblack@eecs.umich.edu if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) { 48011147Smitch.hayenga@arm.com return 0; 48111147Smitch.hayenga@arm.com } 48211147Smitch.hayenga@arm.com ready_inst = true; 4835728Sgblack@eecs.umich.edu } else if (type == I_SHARED && (IS_OT_READ_LM(ii->opType()) || 4848105Sgblack@eecs.umich.edu IS_OT_WRITE_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType()))) { 4859180Sandreas.hansson@arm.com // Here for Shared memory instruction 4869179Sandreas.hansson@arm.com if (IS_OT_READ_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType())) { 4875728Sgblack@eecs.umich.edu if ((outstandingReqsWrLm + wrLmReqsInPipe) > 0) { 4885728Sgblack@eecs.umich.edu return 0; 4898975Sandreas.hansson@arm.com } 4905728Sgblack@eecs.umich.edu } 4915728Sgblack@eecs.umich.edu 4925728Sgblack@eecs.umich.edu if (IS_OT_WRITE_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType()) || 4935728Sgblack@eecs.umich.edu IS_OT_HIST_LM(ii->opType())) { 4945728Sgblack@eecs.umich.edu if ((outstandingReqsRdLm + rdLmReqsInPipe) > 0) { 4955728Sgblack@eecs.umich.edu return 0; 4965728Sgblack@eecs.umich.edu } 4975728Sgblack@eecs.umich.edu } 4982623SN/A 4992623SN/A if (!locMemBusRdy) { 5008444Sgblack@eecs.umich.edu // Is there an available VRF->LDS read bus? 50111608Snikos.nikoleris@arm.com return 0; 5022623SN/A } 50311147Smitch.hayenga@arm.com if (!locMemIssueRdy) { 50411147Smitch.hayenga@arm.com // Is wave slot free? 50511147Smitch.hayenga@arm.com return 0; 5068443Sgblack@eecs.umich.edu } 5075728Sgblack@eecs.umich.edu 5087720Sgblack@eecs.umich.edu if (!computeUnit->localMemoryPipe. 5099814Sandreas.hansson@arm.com isLMReqFIFOWrRdy(rdLmReqsInPipe + wrLmReqsInPipe)) { 5106973Stjones1@inf.ed.ac.uk // Can we insert a new request to the LDS Request FIFO? 5113169Sstever@eecs.umich.edu return 0; 51210031SAli.Saidi@ARM.com } 51310031SAli.Saidi@ARM.com // can we schedule source & destination operands on the VRF? 51410031SAli.Saidi@ARM.com if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii, 51510031SAli.Saidi@ARM.com VrfAccessType::RD_WR)) { 51610031SAli.Saidi@ARM.com return 0; 51710031SAli.Saidi@ARM.com } 51810031SAli.Saidi@ARM.com if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) { 51910031SAli.Saidi@ARM.com return 0; 52010665SAli.Saidi@ARM.com } 52110665SAli.Saidi@ARM.com ready_inst = true; 5227045Ssteve.reinhardt@amd.com } else if (type == I_PRIVATE && (IS_OT_READ_PM(ii->opType()) || 52311435Smitch.hayenga@arm.com IS_OT_WRITE_PM(ii->opType()) || IS_OT_ATOMIC_PM(ii->opType()))) { 52411435Smitch.hayenga@arm.com // Here for Private memory instruction ------------------------ // 5255728Sgblack@eecs.umich.edu if (IS_OT_READ_PM(ii->opType()) || IS_OT_ATOMIC_PM(ii->opType())) { 52610024Sdam.sunwoo@arm.com if ((outstandingReqsWrGm + wrGmReqsInPipe) > 0) { 52710024Sdam.sunwoo@arm.com return 0; 5287520Sgblack@eecs.umich.edu } 5295744Sgblack@eecs.umich.edu } 5305728Sgblack@eecs.umich.edu 5315894Sgblack@eecs.umich.edu if (IS_OT_WRITE_PM(ii->opType()) || IS_OT_ATOMIC_PM(ii->opType()) || 5325744Sgblack@eecs.umich.edu IS_OT_HIST_PM(ii->opType())) { 5335894Sgblack@eecs.umich.edu if ((outstandingReqsRdGm + rdGmReqsInPipe) > 0) { 5346102Sgblack@eecs.umich.edu return 0; 5355894Sgblack@eecs.umich.edu } 5365894Sgblack@eecs.umich.edu } 5376973Stjones1@inf.ed.ac.uk 5388443Sgblack@eecs.umich.edu if (!glbMemBusRdy) { 5398486Sgblack@eecs.umich.edu // Is there an available VRF->Global memory read bus? 5408486Sgblack@eecs.umich.edu return 0; 5418486Sgblack@eecs.umich.edu } 5428486Sgblack@eecs.umich.edu 5436973Stjones1@inf.ed.ac.uk if (!glbMemIssueRdy) { 54411147Smitch.hayenga@arm.com // Is wave slot free? 54511147Smitch.hayenga@arm.com return 0; 5465744Sgblack@eecs.umich.edu } 5476973Stjones1@inf.ed.ac.uk 5488443Sgblack@eecs.umich.edu if (!computeUnit->globalMemoryPipe. 5498486Sgblack@eecs.umich.edu isGMReqFIFOWrRdy(rdGmReqsInPipe + wrGmReqsInPipe)) { 5508486Sgblack@eecs.umich.edu // Can we insert a new request to the Global Mem Request FIFO? 55111147Smitch.hayenga@arm.com return 0; 5522623SN/A } 5532623SN/A // can we schedule source & destination operands on the VRF? 5547045Ssteve.reinhardt@amd.com if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii, 5555728Sgblack@eecs.umich.edu VrfAccessType::RD_WR)) { 5562623SN/A return 0; 5572623SN/A } 55811148Smitch.hayenga@arm.com if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) { 55911148Smitch.hayenga@arm.com return 0; 56011148Smitch.hayenga@arm.com } 56111148Smitch.hayenga@arm.com ready_inst = true; 56211148Smitch.hayenga@arm.com } else if (type == I_FLAT && IS_OT_FLAT(ii->opType())) { 56311321Ssteve.reinhardt@amd.com if (!glbMemBusRdy) { 56411151Smitch.hayenga@arm.com // Is there an available VRF->Global memory read bus? 56511148Smitch.hayenga@arm.com return 0; 56611148Smitch.hayenga@arm.com } 56711148Smitch.hayenga@arm.com 56811148Smitch.hayenga@arm.com if (!locMemBusRdy) { 56911148Smitch.hayenga@arm.com // Is there an available VRF->LDS read bus? 57011148Smitch.hayenga@arm.com return 0; 5712623SN/A } 5722623SN/A 5736973Stjones1@inf.ed.ac.uk if (!glbMemIssueRdy) { 5746973Stjones1@inf.ed.ac.uk // Is wave slot free? 5759342SAndreas.Sandberg@arm.com return 0; 5766973Stjones1@inf.ed.ac.uk } 5776973Stjones1@inf.ed.ac.uk 5786973Stjones1@inf.ed.ac.uk if (!locMemIssueRdy) { 5796973Stjones1@inf.ed.ac.uk return 0; 5806973Stjones1@inf.ed.ac.uk } 5817691SAli.Saidi@ARM.com if (!computeUnit->globalMemoryPipe. 5826973Stjones1@inf.ed.ac.uk isGMReqFIFOWrRdy(rdGmReqsInPipe + wrGmReqsInPipe)) { 5836973Stjones1@inf.ed.ac.uk // Can we insert a new request to the Global Mem Request FIFO? 5846973Stjones1@inf.ed.ac.uk return 0; 5856973Stjones1@inf.ed.ac.uk } 5866973Stjones1@inf.ed.ac.uk 5876973Stjones1@inf.ed.ac.uk if (!computeUnit->localMemoryPipe. 5886973Stjones1@inf.ed.ac.uk isLMReqFIFOWrRdy(rdLmReqsInPipe + wrLmReqsInPipe)) { 5896973Stjones1@inf.ed.ac.uk // Can we insert a new request to the LDS Request FIFO? 5906973Stjones1@inf.ed.ac.uk return 0; 5916973Stjones1@inf.ed.ac.uk } 5926973Stjones1@inf.ed.ac.uk // can we schedule source & destination operands on the VRF? 5936973Stjones1@inf.ed.ac.uk if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii, 5946973Stjones1@inf.ed.ac.uk VrfAccessType::RD_WR)) { 5956973Stjones1@inf.ed.ac.uk return 0; 5966973Stjones1@inf.ed.ac.uk } 5976973Stjones1@inf.ed.ac.uk // are all the operands ready? (RAW, WAW and WAR depedencies met?) 5986973Stjones1@inf.ed.ac.uk if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) { 5992623SN/A return 0; 6002623SN/A } 60111147Smitch.hayenga@arm.com ready_inst = true; 60211147Smitch.hayenga@arm.com } else { 60311147Smitch.hayenga@arm.com return 0; 60411147Smitch.hayenga@arm.com } 60511147Smitch.hayenga@arm.com 60611147Smitch.hayenga@arm.com assert(ready_inst); 6075221Ssaidi@eecs.umich.edu 6085221Ssaidi@eecs.umich.edu DPRINTF(GPUExec, "CU%d: WF[%d][%d]: Ready Inst : %s\n", computeUnit->cu_id, 60910596Sgabeblack@google.com simdId, wfSlotId, ii->disassemble()); 6103387Sgblack@eecs.umich.edu return 1; 61110596Sgabeblack@google.com} 61210596Sgabeblack@google.com 6135348Ssaidi@eecs.umich.eduvoid 6148143SAli.Saidi@ARM.comWavefront::updateResources() 6158143SAli.Saidi@ARM.com{ 6168143SAli.Saidi@ARM.com // Get current instruction 6178143SAli.Saidi@ARM.com GPUDynInstPtr ii = instructionBuffer.front(); 6187720Sgblack@eecs.umich.edu assert(ii); 61911147Smitch.hayenga@arm.com computeUnit->vrf[simdId]->updateResources(this, ii); 62011147Smitch.hayenga@arm.com // Single precision ALU or Branch or Return or Special instruction 6212623SN/A if (ii->opType() == Enums::OT_ALU || ii->opType() == Enums::OT_SPECIAL || 6227720Sgblack@eecs.umich.edu ii->opType() == Enums::OT_BRANCH || IS_OT_LDAS(ii->opType()) || 6239342SAndreas.Sandberg@arm.com // FIXME: Kernel argument loads are currently treated as ALU operations 6245669Sgblack@eecs.umich.edu // since we don't send memory packets at execution. If we fix that then 62510024Sdam.sunwoo@arm.com // we should map them to one of the memory pipelines 62611435Smitch.hayenga@arm.com ii->opType()==Enums::OT_KERN_READ || 6275894Sgblack@eecs.umich.edu ii->opType()==Enums::OT_ARG || 6288277SAli.Saidi@ARM.com ii->opType()==Enums::OT_RET) { 62911147Smitch.hayenga@arm.com computeUnit->aluPipe[simdId].preset(computeUnit->shader-> 63011147Smitch.hayenga@arm.com ticks(computeUnit->spBypassLength())); 6312623SN/A // this is to enforce a fixed number of cycles per issue slot per SIMD 6325669Sgblack@eecs.umich.edu computeUnit->wfWait[simdId].preset(computeUnit->shader-> 6335669Sgblack@eecs.umich.edu ticks(computeUnit->issuePeriod)); 6345894Sgblack@eecs.umich.edu } else if (ii->opType() == Enums::OT_BARRIER) { 63510464SAndreas.Sandberg@ARM.com computeUnit->wfWait[simdId].preset(computeUnit->shader-> 63612284Sjose.marinho@arm.com ticks(computeUnit->issuePeriod)); 6375894Sgblack@eecs.umich.edu } else if (ii->opType() == Enums::OT_FLAT_READ) { 6385894Sgblack@eecs.umich.edu assert(Enums::SC_NONE != ii->executedAs()); 6395894Sgblack@eecs.umich.edu memReqsInPipe++; 6405894Sgblack@eecs.umich.edu rdGmReqsInPipe++; 6415894Sgblack@eecs.umich.edu if ( Enums::SC_SHARED == ii->executedAs() ) { 64210379Sandreas.hansson@arm.com computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 64310379Sandreas.hansson@arm.com preset(computeUnit->shader->ticks(4)); 6445894Sgblack@eecs.umich.edu computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 6455894Sgblack@eecs.umich.edu preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 6468277SAli.Saidi@ARM.com } else { 6478277SAli.Saidi@ARM.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 6488949Sandreas.hansson@arm.com preset(computeUnit->shader->ticks(4)); 6495894Sgblack@eecs.umich.edu computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 6508277SAli.Saidi@ARM.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 6515894Sgblack@eecs.umich.edu } 6528975Sandreas.hansson@arm.com } else if (ii->opType() == Enums::OT_FLAT_WRITE) { 6535894Sgblack@eecs.umich.edu assert(Enums::SC_NONE != ii->executedAs()); 6545894Sgblack@eecs.umich.edu memReqsInPipe++; 6555894Sgblack@eecs.umich.edu wrGmReqsInPipe++; 6565894Sgblack@eecs.umich.edu if (Enums::SC_SHARED == ii->executedAs()) { 6575894Sgblack@eecs.umich.edu computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 6585894Sgblack@eecs.umich.edu preset(computeUnit->shader->ticks(8)); 6595894Sgblack@eecs.umich.edu computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 6605894Sgblack@eecs.umich.edu preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 6615894Sgblack@eecs.umich.edu } else { 6628277SAli.Saidi@ARM.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 6635894Sgblack@eecs.umich.edu preset(computeUnit->shader->ticks(8)); 6645894Sgblack@eecs.umich.edu computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 6659342SAndreas.Sandberg@arm.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 6665894Sgblack@eecs.umich.edu } 6672623SN/A } else if (IS_OT_READ_GM(ii->opType())) { 6683222Sktlim@umich.edu memReqsInPipe++; 66910464SAndreas.Sandberg@ARM.com rdGmReqsInPipe++; 67012284Sjose.marinho@arm.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 6712623SN/A preset(computeUnit->shader->ticks(4)); 6722623SN/A computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 6732623SN/A preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 6742623SN/A } else if (IS_OT_WRITE_GM(ii->opType())) { 67510379Sandreas.hansson@arm.com memReqsInPipe++; 6762623SN/A wrGmReqsInPipe++; 67711147Smitch.hayenga@arm.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 67811147Smitch.hayenga@arm.com preset(computeUnit->shader->ticks(8)); 6798276SAli.Saidi@ARM.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 6808276SAli.Saidi@ARM.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 6818276SAli.Saidi@ARM.com } else if (IS_OT_ATOMIC_GM(ii->opType())) { 6828276SAli.Saidi@ARM.com memReqsInPipe++; 68311877Sbrandon.potter@amd.com wrGmReqsInPipe++; 68411877Sbrandon.potter@amd.com rdGmReqsInPipe++; 6858276SAli.Saidi@ARM.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 68611877Sbrandon.potter@amd.com preset(computeUnit->shader->ticks(8)); 68711877Sbrandon.potter@amd.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 68811877Sbrandon.potter@amd.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 68911877Sbrandon.potter@amd.com } else if (IS_OT_READ_LM(ii->opType())) { 69011877Sbrandon.potter@amd.com memReqsInPipe++; 69111877Sbrandon.potter@amd.com rdLmReqsInPipe++; 6928276SAli.Saidi@ARM.com computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 6938276SAli.Saidi@ARM.com preset(computeUnit->shader->ticks(4)); 6948276SAli.Saidi@ARM.com computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 6958276SAli.Saidi@ARM.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 6968276SAli.Saidi@ARM.com } else if (IS_OT_WRITE_LM(ii->opType())) { 69711147Smitch.hayenga@arm.com memReqsInPipe++; 6985726Sgblack@eecs.umich.edu wrLmReqsInPipe++; 6992623SN/A computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 7009442SAndreas.Sandberg@ARM.com preset(computeUnit->shader->ticks(8)); 7019442SAndreas.Sandberg@ARM.com computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 7029442SAndreas.Sandberg@ARM.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 7039342SAndreas.Sandberg@arm.com } else if (IS_OT_ATOMIC_LM(ii->opType())) { 7042631SN/A memReqsInPipe++; 7052631SN/A wrLmReqsInPipe++; 7062631SN/A rdLmReqsInPipe++; 7072631SN/A computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 7082631SN/A preset(computeUnit->shader->ticks(8)); 7092623SN/A computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 7102623SN/A preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 7112623SN/A } else if (IS_OT_READ_PM(ii->opType())) { 7122623SN/A memReqsInPipe++; 7133349Sbinkertn@umich.edu rdGmReqsInPipe++; 7142623SN/A computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 71511147Smitch.hayenga@arm.com preset(computeUnit->shader->ticks(4)); 71611147Smitch.hayenga@arm.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 7178277SAli.Saidi@ARM.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 7188277SAli.Saidi@ARM.com } else if (IS_OT_WRITE_PM(ii->opType())) { 7198277SAli.Saidi@ARM.com memReqsInPipe++; 7202623SN/A wrGmReqsInPipe++; 7212623SN/A computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 7225669Sgblack@eecs.umich.edu preset(computeUnit->shader->ticks(8)); 7232623SN/A computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 7242798Sktlim@umich.edu preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 7259342SAndreas.Sandberg@arm.com } else if (IS_OT_ATOMIC_PM(ii->opType())) { 7262644Sstever@eecs.umich.edu memReqsInPipe++; 72710464SAndreas.Sandberg@ARM.com wrGmReqsInPipe++; 72812284Sjose.marinho@arm.com rdGmReqsInPipe++; 7293222Sktlim@umich.edu computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 73010020Smatt.horsnell@ARM.com preset(computeUnit->shader->ticks(8)); 73110020Smatt.horsnell@ARM.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 73210020Smatt.horsnell@ARM.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 73310020Smatt.horsnell@ARM.com } 7342623SN/A} 7357725SAli.Saidi@ARM.com 7362623SN/Avoid 73711147Smitch.hayenga@arm.comWavefront::exec() 7387945SAli.Saidi@ARM.com{ 7397945SAli.Saidi@ARM.com // ---- Exit if wavefront is inactive ----------------------------- // 7407945SAli.Saidi@ARM.com 7417945SAli.Saidi@ARM.com if (status == S_STOPPED || status == S_RETURNING || 7429342SAndreas.Sandberg@arm.com instructionBuffer.empty()) { 7435894Sgblack@eecs.umich.edu return; 7445001Sgblack@eecs.umich.edu } 7455001Sgblack@eecs.umich.edu 7465001Sgblack@eecs.umich.edu // Get current instruction 7473170Sstever@eecs.umich.edu 7484998Sgblack@eecs.umich.edu GPUDynInstPtr ii = instructionBuffer.front(); 7492644Sstever@eecs.umich.edu 7505103Ssaidi@eecs.umich.edu const uint32_t old_pc = pc(); 7515103Ssaidi@eecs.umich.edu DPRINTF(GPUExec, "CU%d: WF[%d][%d]: wave[%d] Executing inst: %s " 7525103Ssaidi@eecs.umich.edu "(pc: %i)\n", computeUnit->cu_id, simdId, wfSlotId, wfDynId, 7535103Ssaidi@eecs.umich.edu ii->disassemble(), old_pc); 7542644Sstever@eecs.umich.edu ii->execute(); 7552644Sstever@eecs.umich.edu // access the VRF 7565726Sgblack@eecs.umich.edu computeUnit->vrf[simdId]->exec(ii, this); 7572623SN/A srcRegOpDist.sample(ii->numSrcRegOperands()); 75811147Smitch.hayenga@arm.com dstRegOpDist.sample(ii->numDstRegOperands()); 7594998Sgblack@eecs.umich.edu computeUnit->numInstrExecuted++; 7604998Sgblack@eecs.umich.edu computeUnit->execRateDist.sample(computeUnit->totalCycles.value() - 7614998Sgblack@eecs.umich.edu computeUnit->lastExecCycle[simdId]); 7624998Sgblack@eecs.umich.edu computeUnit->lastExecCycle[simdId] = computeUnit->totalCycles.value(); 7637655Sali.saidi@arm.com if (pc() == old_pc) { 7645001Sgblack@eecs.umich.edu uint32_t new_pc = old_pc + 1; 7655001Sgblack@eecs.umich.edu // PC not modified by instruction, proceed to next or pop frame 7665001Sgblack@eecs.umich.edu pc(new_pc); 7674998Sgblack@eecs.umich.edu if (new_pc == rpc()) { 7682644Sstever@eecs.umich.edu popFromReconvergenceStack(); 7695103Ssaidi@eecs.umich.edu discardFetch(); 7705103Ssaidi@eecs.umich.edu } else { 77111147Smitch.hayenga@arm.com instructionBuffer.pop_front(); 7725103Ssaidi@eecs.umich.edu } 7732644Sstever@eecs.umich.edu } 7745726Sgblack@eecs.umich.edu 7755726Sgblack@eecs.umich.edu if (computeUnit->shader->hsail_mode==Shader::SIMT) { 7762623SN/A const int num_active_lanes = execMask().count(); 7773658Sktlim@umich.edu computeUnit->controlFlowDivergenceDist.sample(num_active_lanes); 7785669Sgblack@eecs.umich.edu computeUnit->numVecOpsExecuted += num_active_lanes; 7795669Sgblack@eecs.umich.edu if (isGmInstruction(ii)) { 7805669Sgblack@eecs.umich.edu computeUnit->activeLanesPerGMemInstrDist.sample(num_active_lanes); 7815669Sgblack@eecs.umich.edu } else if (isLmInstruction(ii)) { 7822623SN/A computeUnit->activeLanesPerLMemInstrDist.sample(num_active_lanes); 7832623SN/A } 7842948Ssaidi@eecs.umich.edu } 7852948Ssaidi@eecs.umich.edu 7862948Ssaidi@eecs.umich.edu // ---- Update Vector ALU pipeline and other resources ------------------ // 7872948Ssaidi@eecs.umich.edu // Single precision ALU or Branch or Return or Special instruction 7882948Ssaidi@eecs.umich.edu if (ii->opType() == Enums::OT_ALU || ii->opType() == Enums::OT_SPECIAL || 7892623SN/A ii->opType() == Enums::OT_BRANCH || IS_OT_LDAS(ii->opType()) || 7902623SN/A // FIXME: Kernel argument loads are currently treated as ALU operations 7918975Sandreas.hansson@arm.com // since we don't send memory packets at execution. If we fix that then 7922623SN/A // we should map them to one of the memory pipelines 79310669Sandreas.hansson@arm.com ii->opType() == Enums::OT_KERN_READ || 79410669Sandreas.hansson@arm.com ii->opType() == Enums::OT_ARG || 79510669Sandreas.hansson@arm.com ii->opType() == Enums::OT_RET) { 79610669Sandreas.hansson@arm.com computeUnit->aluPipe[simdId].set(computeUnit->shader-> 7979165Sandreas.hansson@arm.com ticks(computeUnit->spBypassLength())); 79810669Sandreas.hansson@arm.com 7998948Sandreas.hansson@arm.com // this is to enforce a fixed number of cycles per issue slot per SIMD 8004433Ssaidi@eecs.umich.edu computeUnit->wfWait[simdId].set(computeUnit->shader-> 8012623SN/A ticks(computeUnit->issuePeriod)); 8022623SN/A } else if (ii->opType() == Enums::OT_BARRIER) { 8032657Ssaidi@eecs.umich.edu computeUnit->wfWait[simdId].set(computeUnit->shader-> 80410713Sandreas.hansson@arm.com ticks(computeUnit->issuePeriod)); 8052623SN/A } else if (ii->opType() == Enums::OT_FLAT_READ) { 8062623SN/A assert(Enums::SC_NONE != ii->executedAs()); 8072623SN/A 8082623SN/A if (Enums::SC_SHARED == ii->executedAs()) { 8092623SN/A computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 8103349Sbinkertn@umich.edu set(computeUnit->shader->ticks(4)); 8118975Sandreas.hansson@arm.com computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 8122657Ssaidi@eecs.umich.edu set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 8132657Ssaidi@eecs.umich.edu } else { 8142657Ssaidi@eecs.umich.edu computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 8152623SN/A set(computeUnit->shader->ticks(4)); 8162623SN/A computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 8172623SN/A set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 8183349Sbinkertn@umich.edu } 8192623SN/A } else if (ii->opType() == Enums::OT_FLAT_WRITE) { 8202623SN/A assert(Enums::SC_NONE != ii->executedAs()); 8212623SN/A if (Enums::SC_SHARED == ii->executedAs()) { 8224870Sstever@eecs.umich.edu computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 8237516Shestness@cs.utexas.edu set(computeUnit->shader->ticks(8)); 8247516Shestness@cs.utexas.edu computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 8252623SN/A set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 82610020Smatt.horsnell@ARM.com } else { 82710464SAndreas.Sandberg@ARM.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 82810464SAndreas.Sandberg@ARM.com set(computeUnit->shader->ticks(8)); 82912284Sjose.marinho@arm.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 8303184Srdreslin@umich.edu set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 8315728Sgblack@eecs.umich.edu } 8325728Sgblack@eecs.umich.edu } else if (IS_OT_READ_GM(ii->opType())) { 8335728Sgblack@eecs.umich.edu computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 8345728Sgblack@eecs.umich.edu set(computeUnit->shader->ticks(4)); 8355728Sgblack@eecs.umich.edu computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 8365728Sgblack@eecs.umich.edu set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 8375728Sgblack@eecs.umich.edu } else if (IS_OT_WRITE_GM(ii->opType())) { 8385728Sgblack@eecs.umich.edu computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 83911320Ssteve.reinhardt@amd.com set(computeUnit->shader->ticks(8)); 8405728Sgblack@eecs.umich.edu computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 8415728Sgblack@eecs.umich.edu set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 8425728Sgblack@eecs.umich.edu } else if (IS_OT_ATOMIC_GM(ii->opType())) { 8435728Sgblack@eecs.umich.edu computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 8445728Sgblack@eecs.umich.edu set(computeUnit->shader->ticks(8)); 8455728Sgblack@eecs.umich.edu computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 8465728Sgblack@eecs.umich.edu set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 8475728Sgblack@eecs.umich.edu } else if (IS_OT_READ_LM(ii->opType())) { 8485728Sgblack@eecs.umich.edu computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 8495728Sgblack@eecs.umich.edu set(computeUnit->shader->ticks(4)); 8505728Sgblack@eecs.umich.edu computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 8515728Sgblack@eecs.umich.edu set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 8525728Sgblack@eecs.umich.edu } else if (IS_OT_WRITE_LM(ii->opType())) { 8535728Sgblack@eecs.umich.edu computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 8545728Sgblack@eecs.umich.edu set(computeUnit->shader->ticks(8)); 8555728Sgblack@eecs.umich.edu computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 8569342SAndreas.Sandberg@arm.com set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 8575728Sgblack@eecs.umich.edu } else if (IS_OT_ATOMIC_LM(ii->opType())) { 85811147Smitch.hayenga@arm.com computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 85911147Smitch.hayenga@arm.com set(computeUnit->shader->ticks(8)); 8602623SN/A computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 8614998Sgblack@eecs.umich.edu set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 8624998Sgblack@eecs.umich.edu } 8634998Sgblack@eecs.umich.edu} 8645001Sgblack@eecs.umich.edu 8655001Sgblack@eecs.umich.edubool 8665001Sgblack@eecs.umich.eduWavefront::waitingAtBarrier(int lane) 8675001Sgblack@eecs.umich.edu{ 8685001Sgblack@eecs.umich.edu return barCnt[lane] < maxBarCnt; 8694998Sgblack@eecs.umich.edu} 8702644Sstever@eecs.umich.edu 8712644Sstever@eecs.umich.eduvoid 8722644Sstever@eecs.umich.eduWavefront::pushToReconvergenceStack(uint32_t pc, uint32_t rpc, 8733184Srdreslin@umich.edu const VectorMask& mask) 8743227Sktlim@umich.edu{ 8752644Sstever@eecs.umich.edu assert(mask.count()); 8762623SN/A reconvergenceStack.emplace(new ReconvergenceStackEntry(pc, rpc, mask)); 8772623SN/A} 87810030SAli.Saidi@ARM.com 87910464SAndreas.Sandberg@ARM.comvoid 88010464SAndreas.Sandberg@ARM.comWavefront::popFromReconvergenceStack() 88110464SAndreas.Sandberg@ARM.com{ 88210464SAndreas.Sandberg@ARM.com assert(!reconvergenceStack.empty()); 88310464SAndreas.Sandberg@ARM.com 88410464SAndreas.Sandberg@ARM.com DPRINTF(WavefrontStack, "[%2d, %2d, %2d, %2d] %s %3i => ", 88510464SAndreas.Sandberg@ARM.com computeUnit->cu_id, simdId, wfSlotId, wfDynId, 88610464SAndreas.Sandberg@ARM.com execMask().to_string<char, std::string::traits_type, 88710464SAndreas.Sandberg@ARM.com std::string::allocator_type>().c_str(), pc()); 88810464SAndreas.Sandberg@ARM.com 88910030SAli.Saidi@ARM.com reconvergenceStack.pop(); 89010030SAli.Saidi@ARM.com 89111148Smitch.hayenga@arm.com DPRINTF(WavefrontStack, "%3i %s\n", pc(), 89211148Smitch.hayenga@arm.com execMask().to_string<char, std::string::traits_type, 89311151Smitch.hayenga@arm.com std::string::allocator_type>().c_str()); 89411148Smitch.hayenga@arm.com 89510529Smorr@cs.wisc.edu} 89611147Smitch.hayenga@arm.com 89711356Skrinat01@arm.comvoid 89811356Skrinat01@arm.comWavefront::discardFetch() 89911356Skrinat01@arm.com{ 90011356Skrinat01@arm.com instructionBuffer.clear(); 90111356Skrinat01@arm.com dropFetch |=pendingFetch; 90211356Skrinat01@arm.com} 90311356Skrinat01@arm.com 90411356Skrinat01@arm.comuint32_t 90511147Smitch.hayenga@arm.comWavefront::pc() const 90610030SAli.Saidi@ARM.com{ 90710030SAli.Saidi@ARM.com return reconvergenceStack.top()->pc; 90810529Smorr@cs.wisc.edu} 90910529Smorr@cs.wisc.edu 91010529Smorr@cs.wisc.eduuint32_t 91111148Smitch.hayenga@arm.comWavefront::rpc() const 91211321Ssteve.reinhardt@amd.com{ 91311151Smitch.hayenga@arm.com return reconvergenceStack.top()->rpc; 91411148Smitch.hayenga@arm.com} 91510529Smorr@cs.wisc.edu 91610529Smorr@cs.wisc.eduVectorMask 91710030SAli.Saidi@ARM.comWavefront::execMask() const 9182623SN/A{ 9198975Sandreas.hansson@arm.com return reconvergenceStack.top()->execMask; 9202623SN/A} 92110669Sandreas.hansson@arm.com 9222948Ssaidi@eecs.umich.edubool 92310669Sandreas.hansson@arm.comWavefront::execMask(int lane) const 92410669Sandreas.hansson@arm.com{ 92510669Sandreas.hansson@arm.com return reconvergenceStack.top()->execMask[lane]; 92610669Sandreas.hansson@arm.com} 92710669Sandreas.hansson@arm.com 92810669Sandreas.hansson@arm.com 9299165Sandreas.hansson@arm.comvoid 93010669Sandreas.hansson@arm.comWavefront::pc(uint32_t new_pc) 93110669Sandreas.hansson@arm.com{ 93210669Sandreas.hansson@arm.com reconvergenceStack.top()->pc = new_pc; 93310713Sandreas.hansson@arm.com} 93410713Sandreas.hansson@arm.com 93510669Sandreas.hansson@arm.comuint32_t 9363310Srdreslin@umich.eduWavefront::getStaticContextSize() const 9372948Ssaidi@eecs.umich.edu{ 9382948Ssaidi@eecs.umich.edu return barCnt.size() * sizeof(int) + sizeof(dynWaveId) + sizeof(maxBarCnt) + 9392948Ssaidi@eecs.umich.edu sizeof(oldBarrierCnt) + sizeof(barrierCnt) + sizeof(wgId) + 9402948Ssaidi@eecs.umich.edu sizeof(computeUnit->cu_id) + sizeof(barrierId) + sizeof(initMask) + 9412948Ssaidi@eecs.umich.edu sizeof(privBase) + sizeof(spillBase) + sizeof(ldsChunk) + 9422630SN/A computeUnit->wfSize() * sizeof(ReconvergenceStackEntry); 9432623SN/A} 9442623SN/A