wavefront.cc revision 11523
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 311308Santhony.gutierrez@amd.com * All rights reserved. 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * For use for simulation and test purposes only 611308Santhony.gutierrez@amd.com * 711308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 811308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are met: 911308Santhony.gutierrez@amd.com * 1011308Santhony.gutierrez@amd.com * 1. Redistributions of source code must retain the above copyright notice, 1111308Santhony.gutierrez@amd.com * this list of conditions and the following disclaimer. 1211308Santhony.gutierrez@amd.com * 1311308Santhony.gutierrez@amd.com * 2. Redistributions in binary form must reproduce the above copyright notice, 1411308Santhony.gutierrez@amd.com * this list of conditions and the following disclaimer in the documentation 1511308Santhony.gutierrez@amd.com * and/or other materials provided with the distribution. 1611308Santhony.gutierrez@amd.com * 1711308Santhony.gutierrez@amd.com * 3. Neither the name of the copyright holder nor the names of its contributors 1811308Santhony.gutierrez@amd.com * may be used to endorse or promote products derived from this software 1911308Santhony.gutierrez@amd.com * without specific prior written permission. 2011308Santhony.gutierrez@amd.com * 2111308Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2211308Santhony.gutierrez@amd.com * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2311308Santhony.gutierrez@amd.com * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2411308Santhony.gutierrez@amd.com * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2511308Santhony.gutierrez@amd.com * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2611308Santhony.gutierrez@amd.com * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2711308Santhony.gutierrez@amd.com * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2811308Santhony.gutierrez@amd.com * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2911308Santhony.gutierrez@amd.com * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3011308Santhony.gutierrez@amd.com * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3111308Santhony.gutierrez@amd.com * POSSIBILITY OF SUCH DAMAGE. 3211308Santhony.gutierrez@amd.com * 3311308Santhony.gutierrez@amd.com * Author: Lisa Hsu 3411308Santhony.gutierrez@amd.com */ 3511308Santhony.gutierrez@amd.com 3611308Santhony.gutierrez@amd.com#include "gpu-compute/wavefront.hh" 3711308Santhony.gutierrez@amd.com 3811308Santhony.gutierrez@amd.com#include "debug/GPUExec.hh" 3911308Santhony.gutierrez@amd.com#include "debug/WavefrontStack.hh" 4011308Santhony.gutierrez@amd.com#include "gpu-compute/code_enums.hh" 4111308Santhony.gutierrez@amd.com#include "gpu-compute/compute_unit.hh" 4211308Santhony.gutierrez@amd.com#include "gpu-compute/gpu_dyn_inst.hh" 4311308Santhony.gutierrez@amd.com#include "gpu-compute/shader.hh" 4411308Santhony.gutierrez@amd.com#include "gpu-compute/vector_register_file.hh" 4511308Santhony.gutierrez@amd.com 4611308Santhony.gutierrez@amd.comWavefront* 4711308Santhony.gutierrez@amd.comWavefrontParams::create() 4811308Santhony.gutierrez@amd.com{ 4911308Santhony.gutierrez@amd.com return new Wavefront(this); 5011308Santhony.gutierrez@amd.com} 5111308Santhony.gutierrez@amd.com 5211308Santhony.gutierrez@amd.comWavefront::Wavefront(const Params *p) 5311308Santhony.gutierrez@amd.com : SimObject(p), callArgMem(nullptr) 5411308Santhony.gutierrez@amd.com{ 5511308Santhony.gutierrez@amd.com last_trace = 0; 5611308Santhony.gutierrez@amd.com simdId = p->simdId; 5711308Santhony.gutierrez@amd.com wfSlotId = p->wf_slot_id; 5811308Santhony.gutierrez@amd.com 5911308Santhony.gutierrez@amd.com status = S_STOPPED; 6011308Santhony.gutierrez@amd.com reservedVectorRegs = 0; 6111308Santhony.gutierrez@amd.com startVgprIndex = 0; 6211308Santhony.gutierrez@amd.com outstanding_reqs = 0; 6311308Santhony.gutierrez@amd.com mem_reqs_in_pipe = 0; 6411308Santhony.gutierrez@amd.com outstanding_reqs_wr_gm = 0; 6511308Santhony.gutierrez@amd.com outstanding_reqs_wr_lm = 0; 6611308Santhony.gutierrez@amd.com outstanding_reqs_rd_gm = 0; 6711308Santhony.gutierrez@amd.com outstanding_reqs_rd_lm = 0; 6811308Santhony.gutierrez@amd.com rd_lm_reqs_in_pipe = 0; 6911308Santhony.gutierrez@amd.com rd_gm_reqs_in_pipe = 0; 7011308Santhony.gutierrez@amd.com wr_lm_reqs_in_pipe = 0; 7111308Santhony.gutierrez@amd.com wr_gm_reqs_in_pipe = 0; 7211308Santhony.gutierrez@amd.com 7311308Santhony.gutierrez@amd.com barrier_cnt = 0; 7411308Santhony.gutierrez@amd.com old_barrier_cnt = 0; 7511308Santhony.gutierrez@amd.com stalledAtBarrier = false; 7611308Santhony.gutierrez@amd.com 7711308Santhony.gutierrez@amd.com mem_trace_busy = 0; 7811308Santhony.gutierrez@amd.com old_vgpr_tcnt = 0xffffffffffffffffll; 7911308Santhony.gutierrez@amd.com old_dgpr_tcnt = 0xffffffffffffffffll; 8011308Santhony.gutierrez@amd.com 8111308Santhony.gutierrez@amd.com pendingFetch = false; 8211308Santhony.gutierrez@amd.com dropFetch = false; 8311308Santhony.gutierrez@amd.com condRegState = new ConditionRegisterState(); 8411308Santhony.gutierrez@amd.com maxSpVgprs = 0; 8511308Santhony.gutierrez@amd.com maxDpVgprs = 0; 8611308Santhony.gutierrez@amd.com} 8711308Santhony.gutierrez@amd.com 8811308Santhony.gutierrez@amd.comvoid 8911308Santhony.gutierrez@amd.comWavefront::regStats() 9011308Santhony.gutierrez@amd.com{ 9111523Sdavid.guillen@arm.com SimObject::regStats(); 9211523Sdavid.guillen@arm.com 9311308Santhony.gutierrez@amd.com srcRegOpDist 9411308Santhony.gutierrez@amd.com .init(0, 4, 2) 9511308Santhony.gutierrez@amd.com .name(name() + ".src_reg_operand_dist") 9611308Santhony.gutierrez@amd.com .desc("number of executed instructions with N source register operands") 9711308Santhony.gutierrez@amd.com ; 9811308Santhony.gutierrez@amd.com 9911308Santhony.gutierrez@amd.com dstRegOpDist 10011308Santhony.gutierrez@amd.com .init(0, 3, 2) 10111308Santhony.gutierrez@amd.com .name(name() + ".dst_reg_operand_dist") 10211308Santhony.gutierrez@amd.com .desc("number of executed instructions with N destination register " 10311308Santhony.gutierrez@amd.com "operands") 10411308Santhony.gutierrez@amd.com ; 10511308Santhony.gutierrez@amd.com 10611308Santhony.gutierrez@amd.com // FIXME: the name of the WF needs to be unique 10711308Santhony.gutierrez@amd.com numTimesBlockedDueWAXDependencies 10811308Santhony.gutierrez@amd.com .name(name() + ".timesBlockedDueWAXDependencies") 10911308Santhony.gutierrez@amd.com .desc("number of times the wf's instructions are blocked due to WAW " 11011308Santhony.gutierrez@amd.com "or WAR dependencies") 11111308Santhony.gutierrez@amd.com ; 11211308Santhony.gutierrez@amd.com 11311308Santhony.gutierrez@amd.com // FIXME: the name of the WF needs to be unique 11411308Santhony.gutierrez@amd.com numTimesBlockedDueRAWDependencies 11511308Santhony.gutierrez@amd.com .name(name() + ".timesBlockedDueRAWDependencies") 11611308Santhony.gutierrez@amd.com .desc("number of times the wf's instructions are blocked due to RAW " 11711308Santhony.gutierrez@amd.com "dependencies") 11811308Santhony.gutierrez@amd.com ; 11911308Santhony.gutierrez@amd.com 12011308Santhony.gutierrez@amd.com // FIXME: the name of the WF needs to be unique 12111308Santhony.gutierrez@amd.com numTimesBlockedDueVrfPortAvail 12211308Santhony.gutierrez@amd.com .name(name() + ".timesBlockedDueVrfPortAvail") 12311308Santhony.gutierrez@amd.com .desc("number of times instructions are blocked due to VRF port " 12411308Santhony.gutierrez@amd.com "availability") 12511308Santhony.gutierrez@amd.com ; 12611308Santhony.gutierrez@amd.com} 12711308Santhony.gutierrez@amd.com 12811308Santhony.gutierrez@amd.comvoid 12911308Santhony.gutierrez@amd.comWavefront::init() 13011308Santhony.gutierrez@amd.com{ 13111308Santhony.gutierrez@amd.com reservedVectorRegs = 0; 13211308Santhony.gutierrez@amd.com startVgprIndex = 0; 13311308Santhony.gutierrez@amd.com} 13411308Santhony.gutierrez@amd.com 13511308Santhony.gutierrez@amd.comvoid 13611308Santhony.gutierrez@amd.comWavefront::resizeRegFiles(int num_cregs, int num_sregs, int num_dregs) 13711308Santhony.gutierrez@amd.com{ 13811308Santhony.gutierrez@amd.com condRegState->init(num_cregs); 13911308Santhony.gutierrez@amd.com maxSpVgprs = num_sregs; 14011308Santhony.gutierrez@amd.com maxDpVgprs = num_dregs; 14111308Santhony.gutierrez@amd.com} 14211308Santhony.gutierrez@amd.com 14311308Santhony.gutierrez@amd.comWavefront::~Wavefront() 14411308Santhony.gutierrez@amd.com{ 14511308Santhony.gutierrez@amd.com if (callArgMem) 14611308Santhony.gutierrez@amd.com delete callArgMem; 14711308Santhony.gutierrez@amd.com} 14811308Santhony.gutierrez@amd.com 14911308Santhony.gutierrez@amd.comvoid 15011308Santhony.gutierrez@amd.comWavefront::start(uint64_t _wfDynId,uint64_t _base_ptr) 15111308Santhony.gutierrez@amd.com{ 15211308Santhony.gutierrez@amd.com wfDynId = _wfDynId; 15311308Santhony.gutierrez@amd.com base_ptr = _base_ptr; 15411308Santhony.gutierrez@amd.com status = S_RUNNING; 15511308Santhony.gutierrez@amd.com} 15611308Santhony.gutierrez@amd.com 15711308Santhony.gutierrez@amd.combool 15811308Santhony.gutierrez@amd.comWavefront::isGmInstruction(GPUDynInstPtr ii) 15911308Santhony.gutierrez@amd.com{ 16011308Santhony.gutierrez@amd.com if (IS_OT_READ_PM(ii->opType()) || IS_OT_WRITE_PM(ii->opType()) || 16111308Santhony.gutierrez@amd.com IS_OT_ATOMIC_PM(ii->opType())) { 16211308Santhony.gutierrez@amd.com return true; 16311308Santhony.gutierrez@amd.com } 16411308Santhony.gutierrez@amd.com 16511308Santhony.gutierrez@amd.com if (IS_OT_READ_GM(ii->opType()) || IS_OT_WRITE_GM(ii->opType()) || 16611308Santhony.gutierrez@amd.com IS_OT_ATOMIC_GM(ii->opType())) { 16711308Santhony.gutierrez@amd.com return true; 16811308Santhony.gutierrez@amd.com } 16911308Santhony.gutierrez@amd.com 17011308Santhony.gutierrez@amd.com if (IS_OT_FLAT(ii->opType())) { 17111308Santhony.gutierrez@amd.com return true; 17211308Santhony.gutierrez@amd.com } 17311308Santhony.gutierrez@amd.com 17411308Santhony.gutierrez@amd.com return false; 17511308Santhony.gutierrez@amd.com} 17611308Santhony.gutierrez@amd.com 17711308Santhony.gutierrez@amd.combool 17811308Santhony.gutierrez@amd.comWavefront::isLmInstruction(GPUDynInstPtr ii) 17911308Santhony.gutierrez@amd.com{ 18011308Santhony.gutierrez@amd.com if (IS_OT_READ_LM(ii->opType()) || IS_OT_WRITE_LM(ii->opType()) || 18111308Santhony.gutierrez@amd.com IS_OT_ATOMIC_LM(ii->opType())) { 18211308Santhony.gutierrez@amd.com return true; 18311308Santhony.gutierrez@amd.com } 18411308Santhony.gutierrez@amd.com 18511308Santhony.gutierrez@amd.com return false; 18611308Santhony.gutierrez@amd.com} 18711308Santhony.gutierrez@amd.com 18811308Santhony.gutierrez@amd.combool 18911308Santhony.gutierrez@amd.comWavefront::isOldestInstALU() 19011308Santhony.gutierrez@amd.com{ 19111308Santhony.gutierrez@amd.com assert(!instructionBuffer.empty()); 19211308Santhony.gutierrez@amd.com GPUDynInstPtr ii = instructionBuffer.front(); 19311308Santhony.gutierrez@amd.com 19411308Santhony.gutierrez@amd.com if (status != S_STOPPED && (ii->opType() == Enums::OT_NOP || 19511308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_RET || ii->opType() == Enums::OT_BRANCH || 19611308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_ALU || IS_OT_LDAS(ii->opType()) || 19711308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_KERN_READ)) { 19811308Santhony.gutierrez@amd.com return true; 19911308Santhony.gutierrez@amd.com } 20011308Santhony.gutierrez@amd.com 20111308Santhony.gutierrez@amd.com return false; 20211308Santhony.gutierrez@amd.com} 20311308Santhony.gutierrez@amd.com 20411308Santhony.gutierrez@amd.combool 20511308Santhony.gutierrez@amd.comWavefront::isOldestInstBarrier() 20611308Santhony.gutierrez@amd.com{ 20711308Santhony.gutierrez@amd.com assert(!instructionBuffer.empty()); 20811308Santhony.gutierrez@amd.com GPUDynInstPtr ii = instructionBuffer.front(); 20911308Santhony.gutierrez@amd.com 21011308Santhony.gutierrez@amd.com if (status != S_STOPPED && ii->opType() == Enums::OT_BARRIER) { 21111308Santhony.gutierrez@amd.com return true; 21211308Santhony.gutierrez@amd.com } 21311308Santhony.gutierrez@amd.com 21411308Santhony.gutierrez@amd.com return false; 21511308Santhony.gutierrez@amd.com} 21611308Santhony.gutierrez@amd.com 21711308Santhony.gutierrez@amd.combool 21811308Santhony.gutierrez@amd.comWavefront::isOldestInstGMem() 21911308Santhony.gutierrez@amd.com{ 22011308Santhony.gutierrez@amd.com assert(!instructionBuffer.empty()); 22111308Santhony.gutierrez@amd.com GPUDynInstPtr ii = instructionBuffer.front(); 22211308Santhony.gutierrez@amd.com 22311308Santhony.gutierrez@amd.com if (status != S_STOPPED && (IS_OT_READ_GM(ii->opType()) || 22411308Santhony.gutierrez@amd.com IS_OT_WRITE_GM(ii->opType()) || IS_OT_ATOMIC_GM(ii->opType()))) { 22511308Santhony.gutierrez@amd.com 22611308Santhony.gutierrez@amd.com return true; 22711308Santhony.gutierrez@amd.com } 22811308Santhony.gutierrez@amd.com 22911308Santhony.gutierrez@amd.com return false; 23011308Santhony.gutierrez@amd.com} 23111308Santhony.gutierrez@amd.com 23211308Santhony.gutierrez@amd.combool 23311308Santhony.gutierrez@amd.comWavefront::isOldestInstLMem() 23411308Santhony.gutierrez@amd.com{ 23511308Santhony.gutierrez@amd.com assert(!instructionBuffer.empty()); 23611308Santhony.gutierrez@amd.com GPUDynInstPtr ii = instructionBuffer.front(); 23711308Santhony.gutierrez@amd.com 23811308Santhony.gutierrez@amd.com if (status != S_STOPPED && (IS_OT_READ_LM(ii->opType()) || 23911308Santhony.gutierrez@amd.com IS_OT_WRITE_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType()))) { 24011308Santhony.gutierrez@amd.com 24111308Santhony.gutierrez@amd.com return true; 24211308Santhony.gutierrez@amd.com } 24311308Santhony.gutierrez@amd.com 24411308Santhony.gutierrez@amd.com return false; 24511308Santhony.gutierrez@amd.com} 24611308Santhony.gutierrez@amd.com 24711308Santhony.gutierrez@amd.combool 24811308Santhony.gutierrez@amd.comWavefront::isOldestInstPrivMem() 24911308Santhony.gutierrez@amd.com{ 25011308Santhony.gutierrez@amd.com assert(!instructionBuffer.empty()); 25111308Santhony.gutierrez@amd.com GPUDynInstPtr ii = instructionBuffer.front(); 25211308Santhony.gutierrez@amd.com 25311308Santhony.gutierrez@amd.com if (status != S_STOPPED && (IS_OT_READ_PM(ii->opType()) || 25411308Santhony.gutierrez@amd.com IS_OT_WRITE_PM(ii->opType()) || IS_OT_ATOMIC_PM(ii->opType()))) { 25511308Santhony.gutierrez@amd.com 25611308Santhony.gutierrez@amd.com return true; 25711308Santhony.gutierrez@amd.com } 25811308Santhony.gutierrez@amd.com 25911308Santhony.gutierrez@amd.com return false; 26011308Santhony.gutierrez@amd.com} 26111308Santhony.gutierrez@amd.com 26211308Santhony.gutierrez@amd.combool 26311308Santhony.gutierrez@amd.comWavefront::isOldestInstFlatMem() 26411308Santhony.gutierrez@amd.com{ 26511308Santhony.gutierrez@amd.com assert(!instructionBuffer.empty()); 26611308Santhony.gutierrez@amd.com GPUDynInstPtr ii = instructionBuffer.front(); 26711308Santhony.gutierrez@amd.com 26811308Santhony.gutierrez@amd.com if (status != S_STOPPED && IS_OT_FLAT(ii->opType())) { 26911308Santhony.gutierrez@amd.com 27011308Santhony.gutierrez@amd.com return true; 27111308Santhony.gutierrez@amd.com } 27211308Santhony.gutierrez@amd.com 27311308Santhony.gutierrez@amd.com return false; 27411308Santhony.gutierrez@amd.com} 27511308Santhony.gutierrez@amd.com 27611308Santhony.gutierrez@amd.com// Return true if the Wavefront's instruction 27711308Santhony.gutierrez@amd.com// buffer has branch instruction. 27811308Santhony.gutierrez@amd.combool 27911308Santhony.gutierrez@amd.comWavefront::instructionBufferHasBranch() 28011308Santhony.gutierrez@amd.com{ 28111308Santhony.gutierrez@amd.com for (auto it : instructionBuffer) { 28211308Santhony.gutierrez@amd.com GPUDynInstPtr ii = it; 28311308Santhony.gutierrez@amd.com 28411308Santhony.gutierrez@amd.com if (ii->opType() == Enums::OT_RET || ii->opType() == Enums::OT_BRANCH) { 28511308Santhony.gutierrez@amd.com return true; 28611308Santhony.gutierrez@amd.com } 28711308Santhony.gutierrez@amd.com } 28811308Santhony.gutierrez@amd.com 28911308Santhony.gutierrez@amd.com return false; 29011308Santhony.gutierrez@amd.com} 29111308Santhony.gutierrez@amd.com 29211308Santhony.gutierrez@amd.com// Remap HSAIL register to physical VGPR. 29311308Santhony.gutierrez@amd.com// HSAIL register = virtual register assigned to an operand by HLC compiler 29411308Santhony.gutierrez@amd.comuint32_t 29511308Santhony.gutierrez@amd.comWavefront::remap(uint32_t vgprIndex, uint32_t size, uint8_t mode) 29611308Santhony.gutierrez@amd.com{ 29711308Santhony.gutierrez@amd.com assert((vgprIndex < reservedVectorRegs) && (reservedVectorRegs > 0)); 29811308Santhony.gutierrez@amd.com // add the offset from where the VGPRs of the wavefront have been assigned 29911308Santhony.gutierrez@amd.com uint32_t physicalVgprIndex = startVgprIndex + vgprIndex; 30011308Santhony.gutierrez@amd.com // HSAIL double precision (DP) register: calculate the physical VGPR index 30111308Santhony.gutierrez@amd.com // assuming that DP registers are placed after SP ones in the VRF. The DP 30211308Santhony.gutierrez@amd.com // and SP VGPR name spaces in HSAIL mode are separate so we need to adjust 30311308Santhony.gutierrez@amd.com // the DP VGPR index before mapping it to the physical VRF address space 30411308Santhony.gutierrez@amd.com if (mode == 1 && size > 4) { 30511308Santhony.gutierrez@amd.com physicalVgprIndex = startVgprIndex + maxSpVgprs + (2 * vgprIndex); 30611308Santhony.gutierrez@amd.com } 30711308Santhony.gutierrez@amd.com 30811308Santhony.gutierrez@amd.com assert((startVgprIndex <= physicalVgprIndex) && 30911308Santhony.gutierrez@amd.com (startVgprIndex + reservedVectorRegs - 1) >= physicalVgprIndex); 31011308Santhony.gutierrez@amd.com 31111308Santhony.gutierrez@amd.com // calculate absolute physical VGPR index 31211308Santhony.gutierrez@amd.com return physicalVgprIndex % computeUnit->vrf[simdId]->numRegs(); 31311308Santhony.gutierrez@amd.com} 31411308Santhony.gutierrez@amd.com 31511308Santhony.gutierrez@amd.com// Return true if this wavefront is ready 31611308Santhony.gutierrez@amd.com// to execute an instruction of the specified type. 31711308Santhony.gutierrez@amd.comint 31811308Santhony.gutierrez@amd.comWavefront::ready(itype_e type) 31911308Santhony.gutierrez@amd.com{ 32011308Santhony.gutierrez@amd.com // Check to make sure wave is running 32111308Santhony.gutierrez@amd.com if (status == S_STOPPED || status == S_RETURNING || 32211308Santhony.gutierrez@amd.com instructionBuffer.empty()) { 32311308Santhony.gutierrez@amd.com return 0; 32411308Santhony.gutierrez@amd.com } 32511308Santhony.gutierrez@amd.com 32611308Santhony.gutierrez@amd.com // Is the wave waiting at a barrier 32711308Santhony.gutierrez@amd.com if (stalledAtBarrier) { 32811308Santhony.gutierrez@amd.com if (!computeUnit->AllAtBarrier(barrier_id,barrier_cnt, 32911308Santhony.gutierrez@amd.com computeUnit->getRefCounter(dispatchid, wg_id))) { 33011308Santhony.gutierrez@amd.com // Are all threads at barrier? 33111308Santhony.gutierrez@amd.com return 0; 33211308Santhony.gutierrez@amd.com } 33311308Santhony.gutierrez@amd.com old_barrier_cnt = barrier_cnt; 33411308Santhony.gutierrez@amd.com stalledAtBarrier = false; 33511308Santhony.gutierrez@amd.com } 33611308Santhony.gutierrez@amd.com 33711308Santhony.gutierrez@amd.com // Read instruction 33811308Santhony.gutierrez@amd.com GPUDynInstPtr ii = instructionBuffer.front(); 33911308Santhony.gutierrez@amd.com 34011308Santhony.gutierrez@amd.com bool ready_inst M5_VAR_USED = false; 34111308Santhony.gutierrez@amd.com bool glbMemBusRdy = false; 34211308Santhony.gutierrez@amd.com bool glbMemIssueRdy = false; 34311308Santhony.gutierrez@amd.com if (type == I_GLOBAL || type == I_FLAT || type == I_PRIVATE) { 34411308Santhony.gutierrez@amd.com for (int j=0; j < computeUnit->numGlbMemUnits; ++j) { 34511308Santhony.gutierrez@amd.com if (computeUnit->vrfToGlobalMemPipeBus[j].prerdy()) 34611308Santhony.gutierrez@amd.com glbMemBusRdy = true; 34711308Santhony.gutierrez@amd.com if (computeUnit->wfWait[j].prerdy()) 34811308Santhony.gutierrez@amd.com glbMemIssueRdy = true; 34911308Santhony.gutierrez@amd.com } 35011308Santhony.gutierrez@amd.com } 35111308Santhony.gutierrez@amd.com bool locMemBusRdy = false; 35211308Santhony.gutierrez@amd.com bool locMemIssueRdy = false; 35311345Sjohn.kalamatianos@amd.com if (type == I_SHARED || type == I_FLAT) { 35411308Santhony.gutierrez@amd.com for (int j=0; j < computeUnit->numLocMemUnits; ++j) { 35511308Santhony.gutierrez@amd.com if (computeUnit->vrfToLocalMemPipeBus[j].prerdy()) 35611308Santhony.gutierrez@amd.com locMemBusRdy = true; 35711308Santhony.gutierrez@amd.com if (computeUnit->wfWait[j].prerdy()) 35811308Santhony.gutierrez@amd.com locMemIssueRdy = true; 35911308Santhony.gutierrez@amd.com } 36011308Santhony.gutierrez@amd.com } 36111308Santhony.gutierrez@amd.com 36211308Santhony.gutierrez@amd.com // The following code is very error prone and the entire process for 36311308Santhony.gutierrez@amd.com // checking readiness will be fixed eventually. In the meantime, let's 36411308Santhony.gutierrez@amd.com // make sure that we do not silently let an instruction type slip 36511308Santhony.gutierrez@amd.com // through this logic and always return not ready. 36611308Santhony.gutierrez@amd.com if (!(ii->opType() == Enums::OT_BARRIER || ii->opType() == Enums::OT_NOP || 36711308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_RET || ii->opType() == Enums::OT_BRANCH || 36811308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_ALU || IS_OT_LDAS(ii->opType()) || 36911308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_KERN_READ || 37011308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_ARG || 37111308Santhony.gutierrez@amd.com IS_OT_READ_GM(ii->opType()) || IS_OT_WRITE_GM(ii->opType()) || 37211308Santhony.gutierrez@amd.com IS_OT_ATOMIC_GM(ii->opType()) || IS_OT_READ_LM(ii->opType()) || 37311308Santhony.gutierrez@amd.com IS_OT_WRITE_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType()) || 37411308Santhony.gutierrez@amd.com IS_OT_READ_PM(ii->opType()) || IS_OT_WRITE_PM(ii->opType()) || 37511308Santhony.gutierrez@amd.com IS_OT_ATOMIC_PM(ii->opType()) || IS_OT_FLAT(ii->opType()))) { 37611308Santhony.gutierrez@amd.com panic("next instruction: %s is of unknown type\n", ii->disassemble()); 37711308Santhony.gutierrez@amd.com } 37811308Santhony.gutierrez@amd.com 37911308Santhony.gutierrez@amd.com DPRINTF(GPUExec, "CU%d: WF[%d][%d]: Checking Read for Inst : %s\n", 38011308Santhony.gutierrez@amd.com computeUnit->cu_id, simdId, wfSlotId, ii->disassemble()); 38111308Santhony.gutierrez@amd.com 38211308Santhony.gutierrez@amd.com if (type == I_ALU && ii->opType() == Enums::OT_BARRIER) { 38311308Santhony.gutierrez@amd.com // Here for ALU instruction (barrier) 38411308Santhony.gutierrez@amd.com if (!computeUnit->wfWait[simdId].prerdy()) { 38511308Santhony.gutierrez@amd.com // Is wave slot free? 38611308Santhony.gutierrez@amd.com return 0; 38711308Santhony.gutierrez@amd.com } 38811308Santhony.gutierrez@amd.com 38911308Santhony.gutierrez@amd.com // Are there in pipe or outstanding memory requests? 39011308Santhony.gutierrez@amd.com if ((outstanding_reqs + mem_reqs_in_pipe) > 0) { 39111308Santhony.gutierrez@amd.com return 0; 39211308Santhony.gutierrez@amd.com } 39311308Santhony.gutierrez@amd.com 39411308Santhony.gutierrez@amd.com ready_inst = true; 39511308Santhony.gutierrez@amd.com } else if (type == I_ALU && ii->opType() == Enums::OT_NOP) { 39611308Santhony.gutierrez@amd.com // Here for ALU instruction (nop) 39711308Santhony.gutierrez@amd.com if (!computeUnit->wfWait[simdId].prerdy()) { 39811308Santhony.gutierrez@amd.com // Is wave slot free? 39911308Santhony.gutierrez@amd.com return 0; 40011308Santhony.gutierrez@amd.com } 40111308Santhony.gutierrez@amd.com 40211308Santhony.gutierrez@amd.com ready_inst = true; 40311308Santhony.gutierrez@amd.com } else if (type == I_ALU && ii->opType() == Enums::OT_RET) { 40411308Santhony.gutierrez@amd.com // Here for ALU instruction (return) 40511308Santhony.gutierrez@amd.com if (!computeUnit->wfWait[simdId].prerdy()) { 40611308Santhony.gutierrez@amd.com // Is wave slot free? 40711308Santhony.gutierrez@amd.com return 0; 40811308Santhony.gutierrez@amd.com } 40911308Santhony.gutierrez@amd.com 41011308Santhony.gutierrez@amd.com // Are there in pipe or outstanding memory requests? 41111308Santhony.gutierrez@amd.com if ((outstanding_reqs + mem_reqs_in_pipe) > 0) { 41211308Santhony.gutierrez@amd.com return 0; 41311308Santhony.gutierrez@amd.com } 41411308Santhony.gutierrez@amd.com 41511308Santhony.gutierrez@amd.com ready_inst = true; 41611308Santhony.gutierrez@amd.com } else if (type == I_ALU && (ii->opType() == Enums::OT_BRANCH || 41711308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_ALU || IS_OT_LDAS(ii->opType()) || 41811308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_KERN_READ || 41911308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_ARG)) { 42011308Santhony.gutierrez@amd.com // Here for ALU instruction (all others) 42111308Santhony.gutierrez@amd.com if (!computeUnit->wfWait[simdId].prerdy()) { 42211308Santhony.gutierrez@amd.com // Is alu slot free? 42311308Santhony.gutierrez@amd.com return 0; 42411308Santhony.gutierrez@amd.com } 42511308Santhony.gutierrez@amd.com if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii, 42611308Santhony.gutierrez@amd.com VrfAccessType::RD_WR)) { 42711308Santhony.gutierrez@amd.com return 0; 42811308Santhony.gutierrez@amd.com } 42911308Santhony.gutierrez@amd.com 43011308Santhony.gutierrez@amd.com if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) { 43111308Santhony.gutierrez@amd.com return 0; 43211308Santhony.gutierrez@amd.com } 43311308Santhony.gutierrez@amd.com ready_inst = true; 43411308Santhony.gutierrez@amd.com } else if (type == I_GLOBAL && (IS_OT_READ_GM(ii->opType()) || 43511308Santhony.gutierrez@amd.com IS_OT_WRITE_GM(ii->opType()) || IS_OT_ATOMIC_GM(ii->opType()))) { 43611308Santhony.gutierrez@amd.com // Here Global memory instruction 43711308Santhony.gutierrez@amd.com if (IS_OT_READ_GM(ii->opType()) || IS_OT_ATOMIC_GM(ii->opType())) { 43811308Santhony.gutierrez@amd.com // Are there in pipe or outstanding global memory write requests? 43911308Santhony.gutierrez@amd.com if ((outstanding_reqs_wr_gm + wr_gm_reqs_in_pipe) > 0) { 44011308Santhony.gutierrez@amd.com return 0; 44111308Santhony.gutierrez@amd.com } 44211308Santhony.gutierrez@amd.com } 44311308Santhony.gutierrez@amd.com 44411308Santhony.gutierrez@amd.com if (IS_OT_WRITE_GM(ii->opType()) || IS_OT_ATOMIC_GM(ii->opType()) || 44511308Santhony.gutierrez@amd.com IS_OT_HIST_GM(ii->opType())) { 44611308Santhony.gutierrez@amd.com // Are there in pipe or outstanding global memory read requests? 44711308Santhony.gutierrez@amd.com if ((outstanding_reqs_rd_gm + rd_gm_reqs_in_pipe) > 0) 44811308Santhony.gutierrez@amd.com return 0; 44911308Santhony.gutierrez@amd.com } 45011308Santhony.gutierrez@amd.com 45111308Santhony.gutierrez@amd.com if (!glbMemIssueRdy) { 45211308Santhony.gutierrez@amd.com // Is WV issue slot free? 45311308Santhony.gutierrez@amd.com return 0; 45411308Santhony.gutierrez@amd.com } 45511308Santhony.gutierrez@amd.com 45611308Santhony.gutierrez@amd.com if (!glbMemBusRdy) { 45711308Santhony.gutierrez@amd.com // Is there an available VRF->Global memory read bus? 45811308Santhony.gutierrez@amd.com return 0; 45911308Santhony.gutierrez@amd.com } 46011308Santhony.gutierrez@amd.com 46111308Santhony.gutierrez@amd.com if (!computeUnit->globalMemoryPipe. 46211308Santhony.gutierrez@amd.com isGMReqFIFOWrRdy(rd_gm_reqs_in_pipe + wr_gm_reqs_in_pipe)) { 46311308Santhony.gutierrez@amd.com // Can we insert a new request to the Global Mem Request FIFO? 46411308Santhony.gutierrez@amd.com return 0; 46511308Santhony.gutierrez@amd.com } 46611308Santhony.gutierrez@amd.com // can we schedule source & destination operands on the VRF? 46711308Santhony.gutierrez@amd.com if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii, 46811308Santhony.gutierrez@amd.com VrfAccessType::RD_WR)) { 46911308Santhony.gutierrez@amd.com return 0; 47011308Santhony.gutierrez@amd.com } 47111308Santhony.gutierrez@amd.com if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) { 47211308Santhony.gutierrez@amd.com return 0; 47311308Santhony.gutierrez@amd.com } 47411308Santhony.gutierrez@amd.com ready_inst = true; 47511308Santhony.gutierrez@amd.com } else if (type == I_SHARED && (IS_OT_READ_LM(ii->opType()) || 47611308Santhony.gutierrez@amd.com IS_OT_WRITE_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType()))) { 47711308Santhony.gutierrez@amd.com // Here for Shared memory instruction 47811308Santhony.gutierrez@amd.com if (IS_OT_READ_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType())) { 47911308Santhony.gutierrez@amd.com if ((outstanding_reqs_wr_lm + wr_lm_reqs_in_pipe) > 0) { 48011308Santhony.gutierrez@amd.com return 0; 48111308Santhony.gutierrez@amd.com } 48211308Santhony.gutierrez@amd.com } 48311308Santhony.gutierrez@amd.com 48411308Santhony.gutierrez@amd.com if (IS_OT_WRITE_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType()) || 48511308Santhony.gutierrez@amd.com IS_OT_HIST_LM(ii->opType())) { 48611308Santhony.gutierrez@amd.com if ((outstanding_reqs_rd_lm + rd_lm_reqs_in_pipe) > 0) { 48711308Santhony.gutierrez@amd.com return 0; 48811308Santhony.gutierrez@amd.com } 48911308Santhony.gutierrez@amd.com } 49011308Santhony.gutierrez@amd.com 49111308Santhony.gutierrez@amd.com if (!locMemBusRdy) { 49211308Santhony.gutierrez@amd.com // Is there an available VRF->LDS read bus? 49311308Santhony.gutierrez@amd.com return 0; 49411308Santhony.gutierrez@amd.com } 49511308Santhony.gutierrez@amd.com if (!locMemIssueRdy) { 49611308Santhony.gutierrez@amd.com // Is wave slot free? 49711308Santhony.gutierrez@amd.com return 0; 49811308Santhony.gutierrez@amd.com } 49911308Santhony.gutierrez@amd.com 50011308Santhony.gutierrez@amd.com if (!computeUnit->localMemoryPipe. 50111308Santhony.gutierrez@amd.com isLMReqFIFOWrRdy(rd_lm_reqs_in_pipe + wr_lm_reqs_in_pipe)) { 50211308Santhony.gutierrez@amd.com // Can we insert a new request to the LDS Request FIFO? 50311308Santhony.gutierrez@amd.com return 0; 50411308Santhony.gutierrez@amd.com } 50511308Santhony.gutierrez@amd.com // can we schedule source & destination operands on the VRF? 50611308Santhony.gutierrez@amd.com if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii, 50711308Santhony.gutierrez@amd.com VrfAccessType::RD_WR)) { 50811308Santhony.gutierrez@amd.com return 0; 50911308Santhony.gutierrez@amd.com } 51011308Santhony.gutierrez@amd.com if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) { 51111308Santhony.gutierrez@amd.com return 0; 51211308Santhony.gutierrez@amd.com } 51311308Santhony.gutierrez@amd.com ready_inst = true; 51411308Santhony.gutierrez@amd.com } else if (type == I_PRIVATE && (IS_OT_READ_PM(ii->opType()) || 51511308Santhony.gutierrez@amd.com IS_OT_WRITE_PM(ii->opType()) || IS_OT_ATOMIC_PM(ii->opType()))) { 51611308Santhony.gutierrez@amd.com // Here for Private memory instruction ------------------------ // 51711308Santhony.gutierrez@amd.com if (IS_OT_READ_PM(ii->opType()) || IS_OT_ATOMIC_PM(ii->opType())) { 51811308Santhony.gutierrez@amd.com if ((outstanding_reqs_wr_gm + wr_gm_reqs_in_pipe) > 0) { 51911308Santhony.gutierrez@amd.com return 0; 52011308Santhony.gutierrez@amd.com } 52111308Santhony.gutierrez@amd.com } 52211308Santhony.gutierrez@amd.com 52311308Santhony.gutierrez@amd.com if (IS_OT_WRITE_PM(ii->opType()) || IS_OT_ATOMIC_PM(ii->opType()) || 52411308Santhony.gutierrez@amd.com IS_OT_HIST_PM(ii->opType())) { 52511308Santhony.gutierrez@amd.com if ((outstanding_reqs_rd_gm + rd_gm_reqs_in_pipe) > 0) { 52611308Santhony.gutierrez@amd.com return 0; 52711308Santhony.gutierrez@amd.com } 52811308Santhony.gutierrez@amd.com } 52911308Santhony.gutierrez@amd.com 53011308Santhony.gutierrez@amd.com if (!glbMemBusRdy) { 53111308Santhony.gutierrez@amd.com // Is there an available VRF->Global memory read bus? 53211308Santhony.gutierrez@amd.com return 0; 53311308Santhony.gutierrez@amd.com } 53411308Santhony.gutierrez@amd.com 53511308Santhony.gutierrez@amd.com if (!glbMemIssueRdy) { 53611308Santhony.gutierrez@amd.com // Is wave slot free? 53711308Santhony.gutierrez@amd.com return 0; 53811308Santhony.gutierrez@amd.com } 53911308Santhony.gutierrez@amd.com 54011308Santhony.gutierrez@amd.com if (!computeUnit->globalMemoryPipe. 54111308Santhony.gutierrez@amd.com isGMReqFIFOWrRdy(rd_gm_reqs_in_pipe + wr_gm_reqs_in_pipe)) { 54211308Santhony.gutierrez@amd.com // Can we insert a new request to the Global Mem Request FIFO? 54311308Santhony.gutierrez@amd.com return 0; 54411308Santhony.gutierrez@amd.com } 54511308Santhony.gutierrez@amd.com // can we schedule source & destination operands on the VRF? 54611308Santhony.gutierrez@amd.com if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii, 54711308Santhony.gutierrez@amd.com VrfAccessType::RD_WR)) { 54811308Santhony.gutierrez@amd.com return 0; 54911308Santhony.gutierrez@amd.com } 55011308Santhony.gutierrez@amd.com if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) { 55111308Santhony.gutierrez@amd.com return 0; 55211308Santhony.gutierrez@amd.com } 55311308Santhony.gutierrez@amd.com ready_inst = true; 55411308Santhony.gutierrez@amd.com } else if (type == I_FLAT && IS_OT_FLAT(ii->opType())) { 55511308Santhony.gutierrez@amd.com if (!glbMemBusRdy) { 55611308Santhony.gutierrez@amd.com // Is there an available VRF->Global memory read bus? 55711308Santhony.gutierrez@amd.com return 0; 55811308Santhony.gutierrez@amd.com } 55911308Santhony.gutierrez@amd.com 56011308Santhony.gutierrez@amd.com if (!locMemBusRdy) { 56111308Santhony.gutierrez@amd.com // Is there an available VRF->LDS read bus? 56211308Santhony.gutierrez@amd.com return 0; 56311308Santhony.gutierrez@amd.com } 56411308Santhony.gutierrez@amd.com 56511308Santhony.gutierrez@amd.com if (!glbMemIssueRdy) { 56611308Santhony.gutierrez@amd.com // Is wave slot free? 56711308Santhony.gutierrez@amd.com return 0; 56811308Santhony.gutierrez@amd.com } 56911308Santhony.gutierrez@amd.com 57011308Santhony.gutierrez@amd.com if (!locMemIssueRdy) { 57111308Santhony.gutierrez@amd.com return 0; 57211308Santhony.gutierrez@amd.com } 57311308Santhony.gutierrez@amd.com if (!computeUnit->globalMemoryPipe. 57411308Santhony.gutierrez@amd.com isGMReqFIFOWrRdy(rd_gm_reqs_in_pipe + wr_gm_reqs_in_pipe)) { 57511308Santhony.gutierrez@amd.com // Can we insert a new request to the Global Mem Request FIFO? 57611308Santhony.gutierrez@amd.com return 0; 57711308Santhony.gutierrez@amd.com } 57811308Santhony.gutierrez@amd.com 57911308Santhony.gutierrez@amd.com if (!computeUnit->localMemoryPipe. 58011308Santhony.gutierrez@amd.com isLMReqFIFOWrRdy(rd_lm_reqs_in_pipe + wr_lm_reqs_in_pipe)) { 58111308Santhony.gutierrez@amd.com // Can we insert a new request to the LDS Request FIFO? 58211308Santhony.gutierrez@amd.com return 0; 58311308Santhony.gutierrez@amd.com } 58411308Santhony.gutierrez@amd.com // can we schedule source & destination operands on the VRF? 58511308Santhony.gutierrez@amd.com if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii, 58611308Santhony.gutierrez@amd.com VrfAccessType::RD_WR)) { 58711308Santhony.gutierrez@amd.com return 0; 58811308Santhony.gutierrez@amd.com } 58911308Santhony.gutierrez@amd.com // are all the operands ready? (RAW, WAW and WAR depedencies met?) 59011308Santhony.gutierrez@amd.com if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) { 59111308Santhony.gutierrez@amd.com return 0; 59211308Santhony.gutierrez@amd.com } 59311308Santhony.gutierrez@amd.com ready_inst = true; 59411308Santhony.gutierrez@amd.com } else { 59511308Santhony.gutierrez@amd.com return 0; 59611308Santhony.gutierrez@amd.com } 59711308Santhony.gutierrez@amd.com 59811308Santhony.gutierrez@amd.com assert(ready_inst); 59911308Santhony.gutierrez@amd.com 60011308Santhony.gutierrez@amd.com DPRINTF(GPUExec, "CU%d: WF[%d][%d]: Ready Inst : %s\n", computeUnit->cu_id, 60111308Santhony.gutierrez@amd.com simdId, wfSlotId, ii->disassemble()); 60211308Santhony.gutierrez@amd.com return 1; 60311308Santhony.gutierrez@amd.com} 60411308Santhony.gutierrez@amd.com 60511308Santhony.gutierrez@amd.comvoid 60611308Santhony.gutierrez@amd.comWavefront::updateResources() 60711308Santhony.gutierrez@amd.com{ 60811308Santhony.gutierrez@amd.com // Get current instruction 60911308Santhony.gutierrez@amd.com GPUDynInstPtr ii = instructionBuffer.front(); 61011308Santhony.gutierrez@amd.com assert(ii); 61111308Santhony.gutierrez@amd.com computeUnit->vrf[simdId]->updateResources(this, ii); 61211308Santhony.gutierrez@amd.com // Single precision ALU or Branch or Return or Special instruction 61311308Santhony.gutierrez@amd.com if (ii->opType() == Enums::OT_ALU || ii->opType() == Enums::OT_SPECIAL || 61411308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_BRANCH || IS_OT_LDAS(ii->opType()) || 61511308Santhony.gutierrez@amd.com // FIXME: Kernel argument loads are currently treated as ALU operations 61611308Santhony.gutierrez@amd.com // since we don't send memory packets at execution. If we fix that then 61711308Santhony.gutierrez@amd.com // we should map them to one of the memory pipelines 61811308Santhony.gutierrez@amd.com ii->opType()==Enums::OT_KERN_READ || 61911308Santhony.gutierrez@amd.com ii->opType()==Enums::OT_ARG || 62011308Santhony.gutierrez@amd.com ii->opType()==Enums::OT_RET) { 62111308Santhony.gutierrez@amd.com computeUnit->aluPipe[simdId].preset(computeUnit->shader-> 62211308Santhony.gutierrez@amd.com ticks(computeUnit->spBypassLength())); 62311308Santhony.gutierrez@amd.com // this is to enforce a fixed number of cycles per issue slot per SIMD 62411308Santhony.gutierrez@amd.com computeUnit->wfWait[simdId].preset(computeUnit->shader-> 62511308Santhony.gutierrez@amd.com ticks(computeUnit->issuePeriod)); 62611308Santhony.gutierrez@amd.com } else if (ii->opType() == Enums::OT_BARRIER) { 62711308Santhony.gutierrez@amd.com computeUnit->wfWait[simdId].preset(computeUnit->shader-> 62811308Santhony.gutierrez@amd.com ticks(computeUnit->issuePeriod)); 62911308Santhony.gutierrez@amd.com } else if (ii->opType() == Enums::OT_FLAT_READ) { 63011308Santhony.gutierrez@amd.com assert(Enums::SC_NONE != ii->executedAs()); 63111308Santhony.gutierrez@amd.com mem_reqs_in_pipe++; 63211308Santhony.gutierrez@amd.com rd_gm_reqs_in_pipe++; 63311308Santhony.gutierrez@amd.com if ( Enums::SC_SHARED == ii->executedAs() ) { 63411308Santhony.gutierrez@amd.com computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 63511308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(4)); 63611308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 63711308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 63811308Santhony.gutierrez@amd.com } else { 63911308Santhony.gutierrez@amd.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 64011308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(4)); 64111308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 64211308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 64311308Santhony.gutierrez@amd.com } 64411308Santhony.gutierrez@amd.com } else if (ii->opType() == Enums::OT_FLAT_WRITE) { 64511308Santhony.gutierrez@amd.com assert(Enums::SC_NONE != ii->executedAs()); 64611308Santhony.gutierrez@amd.com mem_reqs_in_pipe++; 64711308Santhony.gutierrez@amd.com wr_gm_reqs_in_pipe++; 64811308Santhony.gutierrez@amd.com if (Enums::SC_SHARED == ii->executedAs()) { 64911308Santhony.gutierrez@amd.com computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 65011308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(8)); 65111308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 65211308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 65311308Santhony.gutierrez@amd.com } else { 65411308Santhony.gutierrez@amd.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 65511308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(8)); 65611308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 65711308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 65811308Santhony.gutierrez@amd.com } 65911308Santhony.gutierrez@amd.com } else if (IS_OT_READ_GM(ii->opType())) { 66011308Santhony.gutierrez@amd.com mem_reqs_in_pipe++; 66111308Santhony.gutierrez@amd.com rd_gm_reqs_in_pipe++; 66211308Santhony.gutierrez@amd.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 66311308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(4)); 66411308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 66511308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 66611308Santhony.gutierrez@amd.com } else if (IS_OT_WRITE_GM(ii->opType())) { 66711308Santhony.gutierrez@amd.com mem_reqs_in_pipe++; 66811308Santhony.gutierrez@amd.com wr_gm_reqs_in_pipe++; 66911308Santhony.gutierrez@amd.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 67011308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(8)); 67111308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 67211308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 67311308Santhony.gutierrez@amd.com } else if (IS_OT_ATOMIC_GM(ii->opType())) { 67411308Santhony.gutierrez@amd.com mem_reqs_in_pipe++; 67511308Santhony.gutierrez@amd.com wr_gm_reqs_in_pipe++; 67611308Santhony.gutierrez@amd.com rd_gm_reqs_in_pipe++; 67711308Santhony.gutierrez@amd.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 67811308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(8)); 67911308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 68011308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 68111308Santhony.gutierrez@amd.com } else if (IS_OT_READ_LM(ii->opType())) { 68211308Santhony.gutierrez@amd.com mem_reqs_in_pipe++; 68311308Santhony.gutierrez@amd.com rd_lm_reqs_in_pipe++; 68411308Santhony.gutierrez@amd.com computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 68511308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(4)); 68611308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 68711308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 68811308Santhony.gutierrez@amd.com } else if (IS_OT_WRITE_LM(ii->opType())) { 68911308Santhony.gutierrez@amd.com mem_reqs_in_pipe++; 69011308Santhony.gutierrez@amd.com wr_lm_reqs_in_pipe++; 69111308Santhony.gutierrez@amd.com computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 69211308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(8)); 69311308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 69411308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 69511308Santhony.gutierrez@amd.com } else if (IS_OT_ATOMIC_LM(ii->opType())) { 69611308Santhony.gutierrez@amd.com mem_reqs_in_pipe++; 69711308Santhony.gutierrez@amd.com wr_lm_reqs_in_pipe++; 69811308Santhony.gutierrez@amd.com rd_lm_reqs_in_pipe++; 69911308Santhony.gutierrez@amd.com computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 70011308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(8)); 70111308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 70211308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 70311308Santhony.gutierrez@amd.com } else if (IS_OT_READ_PM(ii->opType())) { 70411308Santhony.gutierrez@amd.com mem_reqs_in_pipe++; 70511308Santhony.gutierrez@amd.com rd_gm_reqs_in_pipe++; 70611308Santhony.gutierrez@amd.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 70711308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(4)); 70811308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 70911308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 71011308Santhony.gutierrez@amd.com } else if (IS_OT_WRITE_PM(ii->opType())) { 71111308Santhony.gutierrez@amd.com mem_reqs_in_pipe++; 71211308Santhony.gutierrez@amd.com wr_gm_reqs_in_pipe++; 71311308Santhony.gutierrez@amd.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 71411308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(8)); 71511308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 71611308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 71711308Santhony.gutierrez@amd.com } else if (IS_OT_ATOMIC_PM(ii->opType())) { 71811308Santhony.gutierrez@amd.com mem_reqs_in_pipe++; 71911308Santhony.gutierrez@amd.com wr_gm_reqs_in_pipe++; 72011308Santhony.gutierrez@amd.com rd_gm_reqs_in_pipe++; 72111308Santhony.gutierrez@amd.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 72211308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(8)); 72311308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 72411308Santhony.gutierrez@amd.com preset(computeUnit->shader->ticks(computeUnit->issuePeriod)); 72511308Santhony.gutierrez@amd.com } 72611308Santhony.gutierrez@amd.com} 72711308Santhony.gutierrez@amd.com 72811308Santhony.gutierrez@amd.comvoid 72911308Santhony.gutierrez@amd.comWavefront::exec() 73011308Santhony.gutierrez@amd.com{ 73111308Santhony.gutierrez@amd.com // ---- Exit if wavefront is inactive ----------------------------- // 73211308Santhony.gutierrez@amd.com 73311308Santhony.gutierrez@amd.com if (status == S_STOPPED || status == S_RETURNING || 73411308Santhony.gutierrez@amd.com instructionBuffer.empty()) { 73511308Santhony.gutierrez@amd.com return; 73611308Santhony.gutierrez@amd.com } 73711308Santhony.gutierrez@amd.com 73811308Santhony.gutierrez@amd.com // Get current instruction 73911308Santhony.gutierrez@amd.com 74011308Santhony.gutierrez@amd.com GPUDynInstPtr ii = instructionBuffer.front(); 74111308Santhony.gutierrez@amd.com 74211308Santhony.gutierrez@amd.com const uint32_t old_pc = pc(); 74311308Santhony.gutierrez@amd.com DPRINTF(GPUExec, "CU%d: WF[%d][%d]: wave[%d] Executing inst: %s " 74411308Santhony.gutierrez@amd.com "(pc: %i)\n", computeUnit->cu_id, simdId, wfSlotId, wfDynId, 74511308Santhony.gutierrez@amd.com ii->disassemble(), old_pc); 74611308Santhony.gutierrez@amd.com ii->execute(); 74711308Santhony.gutierrez@amd.com // access the VRF 74811308Santhony.gutierrez@amd.com computeUnit->vrf[simdId]->exec(ii, this); 74911308Santhony.gutierrez@amd.com srcRegOpDist.sample(ii->numSrcRegOperands()); 75011308Santhony.gutierrez@amd.com dstRegOpDist.sample(ii->numDstRegOperands()); 75111308Santhony.gutierrez@amd.com computeUnit->numInstrExecuted++; 75211308Santhony.gutierrez@amd.com computeUnit->execRateDist.sample(computeUnit->totalCycles.value() - 75311308Santhony.gutierrez@amd.com computeUnit->lastExecCycle[simdId]); 75411308Santhony.gutierrez@amd.com computeUnit->lastExecCycle[simdId] = computeUnit->totalCycles.value(); 75511308Santhony.gutierrez@amd.com if (pc() == old_pc) { 75611308Santhony.gutierrez@amd.com uint32_t new_pc = old_pc + 1; 75711308Santhony.gutierrez@amd.com // PC not modified by instruction, proceed to next or pop frame 75811308Santhony.gutierrez@amd.com pc(new_pc); 75911308Santhony.gutierrez@amd.com if (new_pc == rpc()) { 76011308Santhony.gutierrez@amd.com popFromReconvergenceStack(); 76111308Santhony.gutierrez@amd.com discardFetch(); 76211308Santhony.gutierrez@amd.com } else { 76311308Santhony.gutierrez@amd.com instructionBuffer.pop_front(); 76411308Santhony.gutierrez@amd.com } 76511308Santhony.gutierrez@amd.com } 76611308Santhony.gutierrez@amd.com 76711308Santhony.gutierrez@amd.com if (computeUnit->shader->hsail_mode==Shader::SIMT) { 76811308Santhony.gutierrez@amd.com const int num_active_lanes = execMask().count(); 76911308Santhony.gutierrez@amd.com computeUnit->controlFlowDivergenceDist.sample(num_active_lanes); 77011308Santhony.gutierrez@amd.com computeUnit->numVecOpsExecuted += num_active_lanes; 77111308Santhony.gutierrez@amd.com if (isGmInstruction(ii)) { 77211308Santhony.gutierrez@amd.com computeUnit->activeLanesPerGMemInstrDist.sample(num_active_lanes); 77311308Santhony.gutierrez@amd.com } else if (isLmInstruction(ii)) { 77411308Santhony.gutierrez@amd.com computeUnit->activeLanesPerLMemInstrDist.sample(num_active_lanes); 77511308Santhony.gutierrez@amd.com } 77611308Santhony.gutierrez@amd.com } 77711308Santhony.gutierrez@amd.com 77811308Santhony.gutierrez@amd.com // ---- Update Vector ALU pipeline and other resources ------------------ // 77911308Santhony.gutierrez@amd.com // Single precision ALU or Branch or Return or Special instruction 78011308Santhony.gutierrez@amd.com if (ii->opType() == Enums::OT_ALU || ii->opType() == Enums::OT_SPECIAL || 78111308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_BRANCH || IS_OT_LDAS(ii->opType()) || 78211308Santhony.gutierrez@amd.com // FIXME: Kernel argument loads are currently treated as ALU operations 78311308Santhony.gutierrez@amd.com // since we don't send memory packets at execution. If we fix that then 78411308Santhony.gutierrez@amd.com // we should map them to one of the memory pipelines 78511308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_KERN_READ || 78611308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_ARG || 78711308Santhony.gutierrez@amd.com ii->opType() == Enums::OT_RET) { 78811308Santhony.gutierrez@amd.com computeUnit->aluPipe[simdId].set(computeUnit->shader-> 78911308Santhony.gutierrez@amd.com ticks(computeUnit->spBypassLength())); 79011308Santhony.gutierrez@amd.com 79111308Santhony.gutierrez@amd.com // this is to enforce a fixed number of cycles per issue slot per SIMD 79211308Santhony.gutierrez@amd.com computeUnit->wfWait[simdId].set(computeUnit->shader-> 79311308Santhony.gutierrez@amd.com ticks(computeUnit->issuePeriod)); 79411308Santhony.gutierrez@amd.com } else if (ii->opType() == Enums::OT_BARRIER) { 79511308Santhony.gutierrez@amd.com computeUnit->wfWait[simdId].set(computeUnit->shader-> 79611308Santhony.gutierrez@amd.com ticks(computeUnit->issuePeriod)); 79711308Santhony.gutierrez@amd.com } else if (ii->opType() == Enums::OT_FLAT_READ) { 79811308Santhony.gutierrez@amd.com assert(Enums::SC_NONE != ii->executedAs()); 79911308Santhony.gutierrez@amd.com 80011308Santhony.gutierrez@amd.com if (Enums::SC_SHARED == ii->executedAs()) { 80111308Santhony.gutierrez@amd.com computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 80211308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(4)); 80311308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 80411308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 80511308Santhony.gutierrez@amd.com } else { 80611308Santhony.gutierrez@amd.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 80711308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(4)); 80811308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 80911308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 81011308Santhony.gutierrez@amd.com } 81111308Santhony.gutierrez@amd.com } else if (ii->opType() == Enums::OT_FLAT_WRITE) { 81211308Santhony.gutierrez@amd.com assert(Enums::SC_NONE != ii->executedAs()); 81311308Santhony.gutierrez@amd.com if (Enums::SC_SHARED == ii->executedAs()) { 81411308Santhony.gutierrez@amd.com computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 81511308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(8)); 81611308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 81711308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 81811308Santhony.gutierrez@amd.com } else { 81911308Santhony.gutierrez@amd.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 82011308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(8)); 82111308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 82211308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 82311308Santhony.gutierrez@amd.com } 82411308Santhony.gutierrez@amd.com } else if (IS_OT_READ_GM(ii->opType())) { 82511308Santhony.gutierrez@amd.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 82611308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(4)); 82711308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 82811308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 82911308Santhony.gutierrez@amd.com } else if (IS_OT_WRITE_GM(ii->opType())) { 83011308Santhony.gutierrez@amd.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 83111308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(8)); 83211308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 83311308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 83411308Santhony.gutierrez@amd.com } else if (IS_OT_ATOMIC_GM(ii->opType())) { 83511308Santhony.gutierrez@amd.com computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()]. 83611308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(8)); 83711308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->GlbMemUnitId()]. 83811308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 83911308Santhony.gutierrez@amd.com } else if (IS_OT_READ_LM(ii->opType())) { 84011308Santhony.gutierrez@amd.com computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 84111308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(4)); 84211308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 84311308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 84411308Santhony.gutierrez@amd.com } else if (IS_OT_WRITE_LM(ii->opType())) { 84511308Santhony.gutierrez@amd.com computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 84611308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(8)); 84711308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 84811308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 84911308Santhony.gutierrez@amd.com } else if (IS_OT_ATOMIC_LM(ii->opType())) { 85011308Santhony.gutierrez@amd.com computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()]. 85111308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(8)); 85211308Santhony.gutierrez@amd.com computeUnit->wfWait[computeUnit->ShrMemUnitId()]. 85311308Santhony.gutierrez@amd.com set(computeUnit->shader->ticks(computeUnit->issuePeriod)); 85411308Santhony.gutierrez@amd.com } 85511308Santhony.gutierrez@amd.com} 85611308Santhony.gutierrez@amd.com 85711308Santhony.gutierrez@amd.combool 85811308Santhony.gutierrez@amd.comWavefront::waitingAtBarrier(int lane) 85911308Santhony.gutierrez@amd.com{ 86011308Santhony.gutierrez@amd.com return bar_cnt[lane] < max_bar_cnt; 86111308Santhony.gutierrez@amd.com} 86211308Santhony.gutierrez@amd.com 86311308Santhony.gutierrez@amd.comvoid 86411308Santhony.gutierrez@amd.comWavefront::pushToReconvergenceStack(uint32_t pc, uint32_t rpc, 86511308Santhony.gutierrez@amd.com const VectorMask& mask) 86611308Santhony.gutierrez@amd.com{ 86711308Santhony.gutierrez@amd.com assert(mask.count()); 86811308Santhony.gutierrez@amd.com reconvergenceStack.emplace(new ReconvergenceStackEntry(pc, rpc, mask)); 86911308Santhony.gutierrez@amd.com} 87011308Santhony.gutierrez@amd.com 87111308Santhony.gutierrez@amd.comvoid 87211308Santhony.gutierrez@amd.comWavefront::popFromReconvergenceStack() 87311308Santhony.gutierrez@amd.com{ 87411308Santhony.gutierrez@amd.com assert(!reconvergenceStack.empty()); 87511308Santhony.gutierrez@amd.com 87611308Santhony.gutierrez@amd.com DPRINTF(WavefrontStack, "[%2d, %2d, %2d, %2d] %s %3i => ", 87711308Santhony.gutierrez@amd.com computeUnit->cu_id, simdId, wfSlotId, wfDynId, 87811308Santhony.gutierrez@amd.com execMask().to_string<char, std::string::traits_type, 87911308Santhony.gutierrez@amd.com std::string::allocator_type>().c_str(), pc()); 88011308Santhony.gutierrez@amd.com 88111308Santhony.gutierrez@amd.com reconvergenceStack.pop(); 88211308Santhony.gutierrez@amd.com 88311308Santhony.gutierrez@amd.com DPRINTF(WavefrontStack, "%3i %s\n", pc(), 88411308Santhony.gutierrez@amd.com execMask().to_string<char, std::string::traits_type, 88511308Santhony.gutierrez@amd.com std::string::allocator_type>().c_str()); 88611308Santhony.gutierrez@amd.com 88711308Santhony.gutierrez@amd.com} 88811308Santhony.gutierrez@amd.com 88911308Santhony.gutierrez@amd.comvoid 89011308Santhony.gutierrez@amd.comWavefront::discardFetch() 89111308Santhony.gutierrez@amd.com{ 89211308Santhony.gutierrez@amd.com instructionBuffer.clear(); 89311308Santhony.gutierrez@amd.com dropFetch |=pendingFetch; 89411308Santhony.gutierrez@amd.com} 89511308Santhony.gutierrez@amd.com 89611308Santhony.gutierrez@amd.comuint32_t 89711308Santhony.gutierrez@amd.comWavefront::pc() const 89811308Santhony.gutierrez@amd.com{ 89911308Santhony.gutierrez@amd.com return reconvergenceStack.top()->pc; 90011308Santhony.gutierrez@amd.com} 90111308Santhony.gutierrez@amd.com 90211308Santhony.gutierrez@amd.comuint32_t 90311308Santhony.gutierrez@amd.comWavefront::rpc() const 90411308Santhony.gutierrez@amd.com{ 90511308Santhony.gutierrez@amd.com return reconvergenceStack.top()->rpc; 90611308Santhony.gutierrez@amd.com} 90711308Santhony.gutierrez@amd.com 90811308Santhony.gutierrez@amd.comVectorMask 90911308Santhony.gutierrez@amd.comWavefront::execMask() const 91011308Santhony.gutierrez@amd.com{ 91111308Santhony.gutierrez@amd.com return reconvergenceStack.top()->execMask; 91211308Santhony.gutierrez@amd.com} 91311308Santhony.gutierrez@amd.com 91411308Santhony.gutierrez@amd.combool 91511308Santhony.gutierrez@amd.comWavefront::execMask(int lane) const 91611308Santhony.gutierrez@amd.com{ 91711308Santhony.gutierrez@amd.com return reconvergenceStack.top()->execMask[lane]; 91811308Santhony.gutierrez@amd.com} 91911308Santhony.gutierrez@amd.com 92011308Santhony.gutierrez@amd.com 92111308Santhony.gutierrez@amd.comvoid 92211308Santhony.gutierrez@amd.comWavefront::pc(uint32_t new_pc) 92311308Santhony.gutierrez@amd.com{ 92411308Santhony.gutierrez@amd.com reconvergenceStack.top()->pc = new_pc; 92511308Santhony.gutierrez@amd.com} 926