vector_register_file.cc revision 11692:e772fdcd3809
12623SN/A/*
210030SAli.Saidi@ARM.com * Copyright (c) 2015 Advanced Micro Devices, Inc.
37725SAli.Saidi@ARM.com * All rights reserved.
47725SAli.Saidi@ARM.com *
57725SAli.Saidi@ARM.com * For use for simulation and test purposes only
67725SAli.Saidi@ARM.com *
77725SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without
87725SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are met:
97725SAli.Saidi@ARM.com *
107725SAli.Saidi@ARM.com * 1. Redistributions of source code must retain the above copyright notice,
117725SAli.Saidi@ARM.com * this list of conditions and the following disclaimer.
127725SAli.Saidi@ARM.com *
137725SAli.Saidi@ARM.com * 2. Redistributions in binary form must reproduce the above copyright notice,
142623SN/A * this list of conditions and the following disclaimer in the documentation
152623SN/A * and/or other materials provided with the distribution.
162623SN/A *
172623SN/A * 3. Neither the name of the copyright holder nor the names of its contributors
182623SN/A * may be used to endorse or promote products derived from this software
192623SN/A * without specific prior written permission.
202623SN/A *
212623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
222623SN/A * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
232623SN/A * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
242623SN/A * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
252623SN/A * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
262623SN/A * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
272623SN/A * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
282623SN/A * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
292623SN/A * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
302623SN/A * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
312623SN/A * POSSIBILITY OF SUCH DAMAGE.
322623SN/A *
332623SN/A * Author: John Kalamatianos
342623SN/A */
352623SN/A
362623SN/A#include "gpu-compute/vector_register_file.hh"
372623SN/A
382623SN/A#include <string>
392665Ssaidi@eecs.umich.edu
402665Ssaidi@eecs.umich.edu#include "base/misc.hh"
412623SN/A#include "gpu-compute/compute_unit.hh"
422623SN/A#include "gpu-compute/gpu_dyn_inst.hh"
433170Sstever@eecs.umich.edu#include "gpu-compute/shader.hh"
448105Sgblack@eecs.umich.edu#include "gpu-compute/simple_pool_manager.hh"
452623SN/A#include "gpu-compute/wavefront.hh"
464040Ssaidi@eecs.umich.edu#include "params/VectorRegisterFile.hh"
476658Snate@binkert.org
488229Snate@binkert.orgVectorRegisterFile::VectorRegisterFile(const VectorRegisterFileParams *p)
492623SN/A    : SimObject(p),
508232Snate@binkert.org      manager(new SimplePoolManager(p->min_alloc, p->num_regs_per_simd)),
519152Satgutier@umich.edu      simdId(p->simd_id), numRegsPerSimd(p->num_regs_per_simd),
528232Snate@binkert.org      vgprState(new VecRegisterState())
538232Snate@binkert.org{
543348Sbinkertn@umich.edu    fatal_if(numRegsPerSimd % 2, "VRF size is illegal\n");
553348Sbinkertn@umich.edu    fatal_if(simdId < 0, "Illegal SIMD id for VRF");
564762Snate@binkert.org
577678Sgblack@eecs.umich.edu    fatal_if(numRegsPerSimd % p->min_alloc, "Min VGPR region allocation is not "
588779Sgblack@eecs.umich.edu             "multiple of VRF size\n");
592901Ssaidi@eecs.umich.edu
602623SN/A    busy.clear();
6110529Smorr@cs.wisc.edu    busy.resize(numRegsPerSimd, 0);
6210529Smorr@cs.wisc.edu    nxtBusy.clear();
632623SN/A    nxtBusy.resize(numRegsPerSimd, 0);
642623SN/A
652623SN/A    vgprState->init(numRegsPerSimd, p->wfSize);
662623SN/A}
672623SN/A
682623SN/Avoid
692623SN/AVectorRegisterFile::setParent(ComputeUnit *_computeUnit)
708921Sandreas.hansson@arm.com{
718921Sandreas.hansson@arm.com    computeUnit = _computeUnit;
728921Sandreas.hansson@arm.com    vgprState->setParent(computeUnit);
738921Sandreas.hansson@arm.com}
749433SAndreas.Sandberg@ARM.com
758779Sgblack@eecs.umich.eduuint8_t
768779Sgblack@eecs.umich.eduVectorRegisterFile::regNxtBusy(int idx, uint32_t operandSize) const
778779Sgblack@eecs.umich.edu{
788779Sgblack@eecs.umich.edu    uint8_t status = nxtBusy.at(idx);
798779Sgblack@eecs.umich.edu
802623SN/A    if (operandSize > 4) {
812623SN/A        status = status | (nxtBusy.at((idx + 1) % numRegs()));
822623SN/A    }
832623SN/A
848707Sandreas.hansson@arm.com    return status;
852948Ssaidi@eecs.umich.edu}
862948Ssaidi@eecs.umich.edu
875606Snate@binkert.orguint8_t
882948Ssaidi@eecs.umich.eduVectorRegisterFile::regBusy(int idx, uint32_t operandSize) const
892948Ssaidi@eecs.umich.edu{
905529Snate@binkert.org    uint8_t status = busy.at(idx);
918707Sandreas.hansson@arm.com
929179Sandreas.hansson@arm.com    if (operandSize > 4) {
939442SAndreas.Sandberg@ARM.com        status = status | (busy.at((idx + 1) % numRegs()));
942623SN/A    }
952623SN/A
963647Srdreslin@umich.edu    return status;
977897Shestness@cs.utexas.edu}
982623SN/A
992623SN/Avoid
1002623SN/AVectorRegisterFile::preMarkReg(int regIdx, uint32_t operandSize, uint8_t value)
10110030SAli.Saidi@ARM.com{
1022623SN/A    nxtBusy.at(regIdx) = value;
1032623SN/A
1042623SN/A    if (operandSize > 4) {
1052623SN/A        nxtBusy.at((regIdx + 1) % numRegs()) = value;
1062901Ssaidi@eecs.umich.edu    }
1079342SAndreas.Sandberg@arm.com}
1082798Sktlim@umich.edu
1099448SAndreas.Sandberg@ARM.comvoid
1109448SAndreas.Sandberg@ARM.comVectorRegisterFile::markReg(int regIdx, uint32_t operandSize, uint8_t value)
1119448SAndreas.Sandberg@ARM.com{
1129448SAndreas.Sandberg@ARM.com    busy.at(regIdx) = value;
1139342SAndreas.Sandberg@arm.com
1149448SAndreas.Sandberg@ARM.com    if (operandSize > 4) {
1159442SAndreas.Sandberg@ARM.com        busy.at((regIdx + 1) % numRegs()) = value;
1162901Ssaidi@eecs.umich.edu    }
1172798Sktlim@umich.edu}
1189342SAndreas.Sandberg@arm.com
1199442SAndreas.Sandberg@ARM.combool
1209442SAndreas.Sandberg@ARM.comVectorRegisterFile::operandsReady(Wavefront *w, GPUDynInstPtr ii) const
1219442SAndreas.Sandberg@ARM.com{
1229442SAndreas.Sandberg@ARM.com    for (int i = 0; i < ii->getNumOperands(); ++i) {
1239442SAndreas.Sandberg@ARM.com        if (ii->isVectorRegister(i)) {
1249448SAndreas.Sandberg@ARM.com            uint32_t vgprIdx = ii->getRegisterIndex(i);
1259648Sdam.sunwoo@arm.com            uint32_t pVgpr = w->remap(vgprIdx, ii->getOperandSize(i), 1);
1269442SAndreas.Sandberg@ARM.com
1272901Ssaidi@eecs.umich.edu            if (regBusy(pVgpr, ii->getOperandSize(i)) == 1) {
1282798Sktlim@umich.edu                if (ii->isDstOperand(i)) {
1292623SN/A                    w->numTimesBlockedDueWAXDependencies++;
1302623SN/A                } else if (ii->isSrcOperand(i)) {
1312623SN/A                    w->numTimesBlockedDueRAWDependencies++;
1329342SAndreas.Sandberg@arm.com                }
1332623SN/A
1349442SAndreas.Sandberg@ARM.com                return false;
1359448SAndreas.Sandberg@ARM.com            }
1369448SAndreas.Sandberg@ARM.com
1379448SAndreas.Sandberg@ARM.com            if (regNxtBusy(pVgpr, ii->getOperandSize(i)) == 1) {
1389442SAndreas.Sandberg@ARM.com                if (ii->isDstOperand(i)) {
1395221Ssaidi@eecs.umich.edu                    w->numTimesBlockedDueWAXDependencies++;
1409523SAndreas.Sandberg@ARM.com                } else if (ii->isSrcOperand(i)) {
1413201Shsul@eecs.umich.edu                    w->numTimesBlockedDueRAWDependencies++;
1429448SAndreas.Sandberg@ARM.com                }
1439448SAndreas.Sandberg@ARM.com
1449448SAndreas.Sandberg@ARM.com                return false;
1459448SAndreas.Sandberg@ARM.com            }
1469448SAndreas.Sandberg@ARM.com        }
1475710Scws3k@cs.virginia.edu    }
1489448SAndreas.Sandberg@ARM.com
1499837Slena@cs.wisc,edu    return true;
1509448SAndreas.Sandberg@ARM.com}
1519448SAndreas.Sandberg@ARM.com
1529837Slena@cs.wisc,eduvoid
1532623SN/AVectorRegisterFile::exec(GPUDynInstPtr ii, Wavefront *w)
1549442SAndreas.Sandberg@ARM.com{
1552798Sktlim@umich.edu    bool loadInstr = ii->isLoad();
1569442SAndreas.Sandberg@ARM.com    bool atomicInstr = ii->isAtomic() || ii->isMemFence();
1579442SAndreas.Sandberg@ARM.com
1589442SAndreas.Sandberg@ARM.com    bool loadNoArgInstr = loadInstr && !ii->isArgLoad();
1599442SAndreas.Sandberg@ARM.com
1609442SAndreas.Sandberg@ARM.com    // iterate over all register destination operands
1619442SAndreas.Sandberg@ARM.com    for (int i = 0; i < ii->getNumOperands(); ++i) {
1629442SAndreas.Sandberg@ARM.com        if (ii->isVectorRegister(i) && ii->isDstOperand(i)) {
1639442SAndreas.Sandberg@ARM.com            uint32_t physReg = w->remap(ii->getRegisterIndex(i),
1649442SAndreas.Sandberg@ARM.com                                        ii->getOperandSize(i), 1);
1659442SAndreas.Sandberg@ARM.com
1669442SAndreas.Sandberg@ARM.com            // mark the destination vector register as busy
1679442SAndreas.Sandberg@ARM.com            markReg(physReg, ii->getOperandSize(i), 1);
1689442SAndreas.Sandberg@ARM.com            // clear the in-flight status of the destination vector register
1699442SAndreas.Sandberg@ARM.com            preMarkReg(physReg, ii->getOperandSize(i), 0);
1709442SAndreas.Sandberg@ARM.com
1712798Sktlim@umich.edu            // FIXME: if we ever model correct timing behavior
1722798Sktlim@umich.edu            // for load argument instructions then we should not
1732798Sktlim@umich.edu            // set the destination register as busy now but when
1742798Sktlim@umich.edu            // the data returns. Loads and Atomics should free
1752798Sktlim@umich.edu            // their destination registers when the data returns,
1769429SAndreas.Sandberg@ARM.com            // not now
1779429SAndreas.Sandberg@ARM.com            if (!atomicInstr && !loadNoArgInstr) {
1789442SAndreas.Sandberg@ARM.com                uint32_t pipeLen = ii->getOperandSize(i) <= 4 ?
1799342SAndreas.Sandberg@arm.com                    computeUnit->spBypassLength() :
1809442SAndreas.Sandberg@ARM.com                    computeUnit->dpBypassLength();
1819442SAndreas.Sandberg@ARM.com
1829442SAndreas.Sandberg@ARM.com                // schedule an event for marking the register as ready
18310464SAndreas.Sandberg@ARM.com                computeUnit->registerEvent(w->simdId, physReg,
1842623SN/A                                           ii->getOperandSize(i),
1852623SN/A                                           computeUnit->shader->tick_cnt +
1862623SN/A                                           computeUnit->shader->ticks(pipeLen),
1872623SN/A                                           0);
1882623SN/A            }
1892623SN/A        }
1909429SAndreas.Sandberg@ARM.com    }
1912623SN/A}
1929179Sandreas.hansson@arm.com
1932623SN/Aint
1942623SN/AVectorRegisterFile::exec(uint64_t dynamic_id, Wavefront *w,
1959523SAndreas.Sandberg@ARM.com                         std::vector<uint32_t> &regVec, uint32_t operandSize,
1969523SAndreas.Sandberg@ARM.com                         uint64_t timestamp)
1979523SAndreas.Sandberg@ARM.com{
1989524SAndreas.Sandberg@ARM.com    int delay = 0;
1999523SAndreas.Sandberg@ARM.com
2009523SAndreas.Sandberg@ARM.com    panic_if(regVec.size() <= 0, "Illegal VGPR vector size=%d\n",
2019523SAndreas.Sandberg@ARM.com             regVec.size());
2029523SAndreas.Sandberg@ARM.com
2032623SN/A    for (int i = 0; i < regVec.size(); ++i) {
2042623SN/A        // mark the destination VGPR as free when the timestamp expires
20510407Smitch.hayenga@arm.com        computeUnit->registerEvent(w->simdId, regVec[i], operandSize,
2062623SN/A                                   computeUnit->shader->tick_cnt + timestamp +
20710407Smitch.hayenga@arm.com                                   computeUnit->shader->ticks(delay), 0);
2085221Ssaidi@eecs.umich.edu    }
2092623SN/A
2102683Sktlim@umich.edu    return delay;
2112623SN/A}
2122623SN/A
2132623SN/Avoid
2149837Slena@cs.wisc,eduVectorRegisterFile::updateResources(Wavefront *w, GPUDynInstPtr ii)
2159342SAndreas.Sandberg@arm.com{
2163686Sktlim@umich.edu    // iterate over all register destination operands
2172623SN/A    for (int i = 0; i < ii->getNumOperands(); ++i) {
21810407Smitch.hayenga@arm.com        if (ii->isVectorRegister(i) && ii->isDstOperand(i)) {
2192623SN/A            uint32_t physReg = w->remap(ii->getRegisterIndex(i),
2202623SN/A                                        ii->getOperandSize(i), 1);
2212623SN/A            // set the in-flight status of the destination vector register
2222623SN/A            preMarkReg(physReg, ii->getOperandSize(i), 1);
2238737Skoansin.tan@gmail.com        }
2242623SN/A    }
2255221Ssaidi@eecs.umich.edu}
2265221Ssaidi@eecs.umich.edu
2272623SN/Abool
2282683Sktlim@umich.eduVectorRegisterFile::vrfOperandAccessReady(uint64_t dynamic_id, Wavefront *w,
2292623SN/A                                          GPUDynInstPtr ii,
2306043Sgblack@eecs.umich.edu                                          VrfAccessType accessType)
2316043Sgblack@eecs.umich.edu{
2326043Sgblack@eecs.umich.edu    bool ready = true;
2339342SAndreas.Sandberg@arm.com
2342623SN/A    return ready;
2352644Sstever@eecs.umich.edu}
2362644Sstever@eecs.umich.edu
2372623SN/Abool
2389837Slena@cs.wisc,eduVectorRegisterFile::vrfOperandAccessReady(Wavefront *w, GPUDynInstPtr ii,
2392623SN/A                                          VrfAccessType accessType)
2402623SN/A{
2412623SN/A    bool ready = true;
2425728Sgblack@eecs.umich.edu
2435728Sgblack@eecs.umich.edu    return ready;
2445728Sgblack@eecs.umich.edu}
2455728Sgblack@eecs.umich.edu
24610533Sali.saidi@arm.comVectorRegisterFile*
24710533Sali.saidi@arm.comVectorRegisterFileParams::create()
24810533Sali.saidi@arm.com{
24910533Sali.saidi@arm.com    return new VectorRegisterFile(this);
25010533Sali.saidi@arm.com}
25110533Sali.saidi@arm.com