vector_register_file.cc revision 11699
112027Sjungma@eit.uni-kl.de/* 212027Sjungma@eit.uni-kl.de * Copyright (c) 2015 Advanced Micro Devices, Inc. 312027Sjungma@eit.uni-kl.de * All rights reserved. 412027Sjungma@eit.uni-kl.de * 512027Sjungma@eit.uni-kl.de * For use for simulation and test purposes only 612027Sjungma@eit.uni-kl.de * 712027Sjungma@eit.uni-kl.de * Redistribution and use in source and binary forms, with or without 812027Sjungma@eit.uni-kl.de * modification, are permitted provided that the following conditions are met: 912027Sjungma@eit.uni-kl.de * 1012027Sjungma@eit.uni-kl.de * 1. Redistributions of source code must retain the above copyright notice, 1112027Sjungma@eit.uni-kl.de * this list of conditions and the following disclaimer. 1212027Sjungma@eit.uni-kl.de * 1312027Sjungma@eit.uni-kl.de * 2. Redistributions in binary form must reproduce the above copyright notice, 1412027Sjungma@eit.uni-kl.de * this list of conditions and the following disclaimer in the documentation 1512027Sjungma@eit.uni-kl.de * and/or other materials provided with the distribution. 1612027Sjungma@eit.uni-kl.de * 1712027Sjungma@eit.uni-kl.de * 3. Neither the name of the copyright holder nor the names of its contributors 1812027Sjungma@eit.uni-kl.de * may be used to endorse or promote products derived from this software 1912027Sjungma@eit.uni-kl.de * without specific prior written permission. 2012027Sjungma@eit.uni-kl.de * 2112027Sjungma@eit.uni-kl.de * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2212027Sjungma@eit.uni-kl.de * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2312027Sjungma@eit.uni-kl.de * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2412027Sjungma@eit.uni-kl.de * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2512027Sjungma@eit.uni-kl.de * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2612027Sjungma@eit.uni-kl.de * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2712027Sjungma@eit.uni-kl.de * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2812027Sjungma@eit.uni-kl.de * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2912027Sjungma@eit.uni-kl.de * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3012027Sjungma@eit.uni-kl.de * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3112027Sjungma@eit.uni-kl.de * POSSIBILITY OF SUCH DAMAGE. 3212027Sjungma@eit.uni-kl.de * 3312027Sjungma@eit.uni-kl.de * Author: John Kalamatianos 3412027Sjungma@eit.uni-kl.de */ 3512027Sjungma@eit.uni-kl.de 3612027Sjungma@eit.uni-kl.de#include "gpu-compute/vector_register_file.hh" 3712027Sjungma@eit.uni-kl.de 3812027Sjungma@eit.uni-kl.de#include <string> 3912027Sjungma@eit.uni-kl.de 4012027Sjungma@eit.uni-kl.de#include "base/misc.hh" 4112027Sjungma@eit.uni-kl.de#include "gpu-compute/compute_unit.hh" 4212027Sjungma@eit.uni-kl.de#include "gpu-compute/gpu_dyn_inst.hh" 4312027Sjungma@eit.uni-kl.de#include "gpu-compute/shader.hh" 4412027Sjungma@eit.uni-kl.de#include "gpu-compute/simple_pool_manager.hh" 4512027Sjungma@eit.uni-kl.de#include "gpu-compute/wavefront.hh" 4612027Sjungma@eit.uni-kl.de#include "params/VectorRegisterFile.hh" 4712027Sjungma@eit.uni-kl.de 4812027Sjungma@eit.uni-kl.deVectorRegisterFile::VectorRegisterFile(const VectorRegisterFileParams *p) 4912027Sjungma@eit.uni-kl.de : SimObject(p), 5012027Sjungma@eit.uni-kl.de manager(new SimplePoolManager(p->min_alloc, p->num_regs_per_simd)), 5112027Sjungma@eit.uni-kl.de simdId(p->simd_id), numRegsPerSimd(p->num_regs_per_simd), 5212027Sjungma@eit.uni-kl.de vgprState(new VecRegisterState()) 5312027Sjungma@eit.uni-kl.de{ 5412027Sjungma@eit.uni-kl.de fatal_if(numRegsPerSimd % 2, "VRF size is illegal\n"); 5512027Sjungma@eit.uni-kl.de fatal_if(simdId < 0, "Illegal SIMD id for VRF"); 5612027Sjungma@eit.uni-kl.de 5712027Sjungma@eit.uni-kl.de fatal_if(numRegsPerSimd % p->min_alloc, "Min VGPR region allocation is not " 5812027Sjungma@eit.uni-kl.de "multiple of VRF size\n"); 5912027Sjungma@eit.uni-kl.de 6012027Sjungma@eit.uni-kl.de busy.clear(); 6112027Sjungma@eit.uni-kl.de busy.resize(numRegsPerSimd, 0); 6212027Sjungma@eit.uni-kl.de nxtBusy.clear(); 6312027Sjungma@eit.uni-kl.de nxtBusy.resize(numRegsPerSimd, 0); 6412027Sjungma@eit.uni-kl.de 6512027Sjungma@eit.uni-kl.de vgprState->init(numRegsPerSimd, p->wfSize); 6612027Sjungma@eit.uni-kl.de} 6712027Sjungma@eit.uni-kl.de 6812027Sjungma@eit.uni-kl.devoid 6912027Sjungma@eit.uni-kl.deVectorRegisterFile::setParent(ComputeUnit *_computeUnit) 7012027Sjungma@eit.uni-kl.de{ 7112027Sjungma@eit.uni-kl.de computeUnit = _computeUnit; 7212027Sjungma@eit.uni-kl.de vgprState->setParent(computeUnit); 7312027Sjungma@eit.uni-kl.de} 7412027Sjungma@eit.uni-kl.de 7512027Sjungma@eit.uni-kl.deuint8_t 7612027Sjungma@eit.uni-kl.deVectorRegisterFile::regNxtBusy(int idx, uint32_t operandSize) const 7712027Sjungma@eit.uni-kl.de{ 7812027Sjungma@eit.uni-kl.de uint8_t status = nxtBusy.at(idx); 7912027Sjungma@eit.uni-kl.de 8012027Sjungma@eit.uni-kl.de if (operandSize > 4) { 8112027Sjungma@eit.uni-kl.de status = status | (nxtBusy.at((idx + 1) % numRegs())); 8212027Sjungma@eit.uni-kl.de } 8312027Sjungma@eit.uni-kl.de 8412027Sjungma@eit.uni-kl.de return status; 8512027Sjungma@eit.uni-kl.de} 8612027Sjungma@eit.uni-kl.de 8712027Sjungma@eit.uni-kl.deuint8_t 8812027Sjungma@eit.uni-kl.deVectorRegisterFile::regBusy(int idx, uint32_t operandSize) const 89{ 90 uint8_t status = busy.at(idx); 91 92 if (operandSize > 4) { 93 status = status | (busy.at((idx + 1) % numRegs())); 94 } 95 96 return status; 97} 98 99void 100VectorRegisterFile::preMarkReg(int regIdx, uint32_t operandSize, uint8_t value) 101{ 102 nxtBusy.at(regIdx) = value; 103 104 if (operandSize > 4) { 105 nxtBusy.at((regIdx + 1) % numRegs()) = value; 106 } 107} 108 109void 110VectorRegisterFile::markReg(int regIdx, uint32_t operandSize, uint8_t value) 111{ 112 busy.at(regIdx) = value; 113 114 if (operandSize > 4) { 115 busy.at((regIdx + 1) % numRegs()) = value; 116 } 117} 118 119bool 120VectorRegisterFile::operandsReady(Wavefront *w, GPUDynInstPtr ii) const 121{ 122 for (int i = 0; i < ii->getNumOperands(); ++i) { 123 if (ii->isVectorRegister(i)) { 124 uint32_t vgprIdx = ii->getRegisterIndex(i, ii); 125 uint32_t pVgpr = w->remap(vgprIdx, ii->getOperandSize(i), 1); 126 127 if (regBusy(pVgpr, ii->getOperandSize(i)) == 1) { 128 if (ii->isDstOperand(i)) { 129 w->numTimesBlockedDueWAXDependencies++; 130 } else if (ii->isSrcOperand(i)) { 131 w->numTimesBlockedDueRAWDependencies++; 132 } 133 134 return false; 135 } 136 137 if (regNxtBusy(pVgpr, ii->getOperandSize(i)) == 1) { 138 if (ii->isDstOperand(i)) { 139 w->numTimesBlockedDueWAXDependencies++; 140 } else if (ii->isSrcOperand(i)) { 141 w->numTimesBlockedDueRAWDependencies++; 142 } 143 144 return false; 145 } 146 } 147 } 148 149 return true; 150} 151 152void 153VectorRegisterFile::exec(GPUDynInstPtr ii, Wavefront *w) 154{ 155 bool loadInstr = ii->isLoad(); 156 bool atomicInstr = ii->isAtomic() || ii->isMemFence(); 157 158 bool loadNoArgInstr = loadInstr && !ii->isArgLoad(); 159 160 // iterate over all register destination operands 161 for (int i = 0; i < ii->getNumOperands(); ++i) { 162 if (ii->isVectorRegister(i) && ii->isDstOperand(i)) { 163 uint32_t physReg = w->remap(ii->getRegisterIndex(i, ii), 164 ii->getOperandSize(i), 1); 165 166 // mark the destination vector register as busy 167 markReg(physReg, ii->getOperandSize(i), 1); 168 // clear the in-flight status of the destination vector register 169 preMarkReg(physReg, ii->getOperandSize(i), 0); 170 171 // FIXME: if we ever model correct timing behavior 172 // for load argument instructions then we should not 173 // set the destination register as busy now but when 174 // the data returns. Loads and Atomics should free 175 // their destination registers when the data returns, 176 // not now 177 if (!atomicInstr && !loadNoArgInstr) { 178 uint32_t pipeLen = ii->getOperandSize(i) <= 4 ? 179 computeUnit->spBypassLength() : 180 computeUnit->dpBypassLength(); 181 182 // schedule an event for marking the register as ready 183 computeUnit->registerEvent(w->simdId, physReg, 184 ii->getOperandSize(i), 185 computeUnit->shader->tick_cnt + 186 computeUnit->shader->ticks(pipeLen), 187 0); 188 } 189 } 190 } 191} 192 193int 194VectorRegisterFile::exec(uint64_t dynamic_id, Wavefront *w, 195 std::vector<uint32_t> ®Vec, uint32_t operandSize, 196 uint64_t timestamp) 197{ 198 int delay = 0; 199 200 panic_if(regVec.size() <= 0, "Illegal VGPR vector size=%d\n", 201 regVec.size()); 202 203 for (int i = 0; i < regVec.size(); ++i) { 204 // mark the destination VGPR as free when the timestamp expires 205 computeUnit->registerEvent(w->simdId, regVec[i], operandSize, 206 computeUnit->shader->tick_cnt + timestamp + 207 computeUnit->shader->ticks(delay), 0); 208 } 209 210 return delay; 211} 212 213void 214VectorRegisterFile::updateResources(Wavefront *w, GPUDynInstPtr ii) 215{ 216 // iterate over all register destination operands 217 for (int i = 0; i < ii->getNumOperands(); ++i) { 218 if (ii->isVectorRegister(i) && ii->isDstOperand(i)) { 219 uint32_t physReg = w->remap(ii->getRegisterIndex(i, ii), 220 ii->getOperandSize(i), 1); 221 // set the in-flight status of the destination vector register 222 preMarkReg(physReg, ii->getOperandSize(i), 1); 223 } 224 } 225} 226 227bool 228VectorRegisterFile::vrfOperandAccessReady(uint64_t dynamic_id, Wavefront *w, 229 GPUDynInstPtr ii, 230 VrfAccessType accessType) 231{ 232 bool ready = true; 233 234 return ready; 235} 236 237bool 238VectorRegisterFile::vrfOperandAccessReady(Wavefront *w, GPUDynInstPtr ii, 239 VrfAccessType accessType) 240{ 241 bool ready = true; 242 243 return ready; 244} 245 246VectorRegisterFile* 247VectorRegisterFileParams::create() 248{ 249 return new VectorRegisterFile(this); 250} 251