global_memory_pipeline.hh revision 11693
1/* 2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * For use for simulation and test purposes only 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the copyright holder nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * Author: John Kalamatianos, Sooraj Puthoor 34 */ 35 36#ifndef __GLOBAL_MEMORY_PIPELINE_HH__ 37#define __GLOBAL_MEMORY_PIPELINE_HH__ 38 39#include <queue> 40#include <string> 41 42#include "gpu-compute/misc.hh" 43#include "params/ComputeUnit.hh" 44#include "sim/stats.hh" 45 46/* 47 * @file global_memory_pipeline.hh 48 * 49 * The global memory pipeline issues newly created global memory packets 50 * from the pipeline to DTLB. The exec() method of the memory packet issues 51 * the packet to the DTLB if there is space available in the return fifo. 52 * This stage also retires previously issued loads and stores that have 53 * returned from the memory sub-system. 54 */ 55 56class ComputeUnit; 57 58class GlobalMemPipeline 59{ 60 public: 61 GlobalMemPipeline(const ComputeUnitParams *params); 62 void init(ComputeUnit *cu); 63 void exec(); 64 65 std::queue<GPUDynInstPtr> &getGMReqFIFO() { return gmIssuedRequests; } 66 std::queue<GPUDynInstPtr> &getGMStRespFIFO() { return gmReturnedStores; } 67 std::queue<GPUDynInstPtr> &getGMLdRespFIFO() { return gmReturnedLoads; } 68 69 bool 70 isGMLdRespFIFOWrRdy() const 71 { 72 return gmReturnedLoads.size() < gmQueueSize; 73 } 74 75 bool 76 isGMStRespFIFOWrRdy() const 77 { 78 return gmReturnedStores.size() < gmQueueSize; 79 } 80 81 bool 82 isGMReqFIFOWrRdy(uint32_t pendReqs=0) const 83 { 84 return (gmIssuedRequests.size() + pendReqs) < gmQueueSize; 85 } 86 87 const std::string &name() const { return _name; } 88 void regStats(); 89 90 void 91 incLoadVRFBankConflictCycles(int num_cycles) 92 { 93 loadVrfBankConflictCycles += num_cycles; 94 } 95 96 private: 97 ComputeUnit *computeUnit; 98 std::string _name; 99 int gmQueueSize; 100 101 // number of cycles of delaying the update of a VGPR that is the 102 // target of a load instruction (or the load component of an atomic) 103 // The delay is due to VRF bank conflicts 104 Stats::Scalar loadVrfBankConflictCycles; 105 // Counters to track the inflight loads and stores 106 // so that we can provide the proper backpressure 107 // on the number of inflight memory operations. 108 int inflightStores; 109 int inflightLoads; 110 111 // The size of global memory. 112 int globalMemSize; 113 114 // Global Memory Request FIFO: all global memory requests 115 // are issued to this FIFO from the memory pipelines 116 std::queue<GPUDynInstPtr> gmIssuedRequests; 117 118 // Globa Store Response FIFO: all responses of global memory 119 // stores are sent to this FIFO from TCP 120 std::queue<GPUDynInstPtr> gmReturnedStores; 121 122 // Global Load Response FIFO: all responses of global memory 123 // loads are sent to this FIFO from TCP 124 std::queue<GPUDynInstPtr> gmReturnedLoads; 125}; 126 127#endif // __GLOBAL_MEMORY_PIPELINE_HH__ 128