compute_unit.cc revision 12717:2e2c211644d2 
1/*
2 * Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * Authors: John Kalamatianos,
34 *          Anthony Gutierrez
35 */
36
37#include "gpu-compute/compute_unit.hh"
38
39#include <limits>
40
41#include "base/output.hh"
42#include "debug/GPUDisp.hh"
43#include "debug/GPUExec.hh"
44#include "debug/GPUFetch.hh"
45#include "debug/GPUMem.hh"
46#include "debug/GPUPort.hh"
47#include "debug/GPUPrefetch.hh"
48#include "debug/GPUSync.hh"
49#include "debug/GPUTLB.hh"
50#include "gpu-compute/dispatcher.hh"
51#include "gpu-compute/gpu_dyn_inst.hh"
52#include "gpu-compute/gpu_static_inst.hh"
53#include "gpu-compute/ndrange.hh"
54#include "gpu-compute/shader.hh"
55#include "gpu-compute/simple_pool_manager.hh"
56#include "gpu-compute/vector_register_file.hh"
57#include "gpu-compute/wavefront.hh"
58#include "mem/page_table.hh"
59#include "sim/process.hh"
60
61ComputeUnit::ComputeUnit(const Params *p) : MemObject(p), fetchStage(p),
62    scoreboardCheckStage(p), scheduleStage(p), execStage(p),
63    globalMemoryPipe(p), localMemoryPipe(p), rrNextMemID(0), rrNextALUWp(0),
64    cu_id(p->cu_id), vrf(p->vector_register_file), numSIMDs(p->num_SIMDs),
65    spBypassPipeLength(p->spbypass_pipe_length),
66    dpBypassPipeLength(p->dpbypass_pipe_length),
67    issuePeriod(p->issue_period),
68    numGlbMemUnits(p->num_global_mem_pipes),
69    numLocMemUnits(p->num_shared_mem_pipes),
70    perLaneTLB(p->perLaneTLB), prefetchDepth(p->prefetch_depth),
71    prefetchStride(p->prefetch_stride), prefetchType(p->prefetch_prev_type),
72    xact_cas_mode(p->xactCasMode), debugSegFault(p->debugSegFault),
73    functionalTLB(p->functionalTLB), localMemBarrier(p->localMemBarrier),
74    countPages(p->countPages), barrier_id(0),
75    vrfToCoalescerBusWidth(p->vrf_to_coalescer_bus_width),
76    coalescerToVrfBusWidth(p->coalescer_to_vrf_bus_width),
77    req_tick_latency(p->mem_req_latency * p->clk_domain->clockPeriod()),
78    resp_tick_latency(p->mem_resp_latency * p->clk_domain->clockPeriod()),
79    _masterId(p->system->getMasterId(this, "ComputeUnit")),
80    lds(*p->localDataStore), _cacheLineSize(p->system->cacheLineSize()),
81    globalSeqNum(0), wavefrontSize(p->wfSize),
82    kernelLaunchInst(new KernelLaunchStaticInst())
83{
84    /**
85     * This check is necessary because std::bitset only provides conversion
86     * to unsigned long or unsigned long long via to_ulong() or to_ullong().
87     * there are * a few places in the code where to_ullong() is used, however
88     * if VSZ is larger than a value the host can support then bitset will
89     * throw a runtime exception. we should remove all use of to_long() or
90     * to_ullong() so we can have VSZ greater than 64b, however until that is
91     * done this assert is required.
92     */
93    fatal_if(p->wfSize > std::numeric_limits<unsigned long long>::digits ||
94             p->wfSize <= 0,
95             "WF size is larger than the host can support");
96    fatal_if(!isPowerOf2(wavefrontSize),
97             "Wavefront size should be a power of 2");
98    // calculate how many cycles a vector load or store will need to transfer
99    // its data over the corresponding buses
100    numCyclesPerStoreTransfer =
101        (uint32_t)ceil((double)(wfSize() * sizeof(uint32_t)) /
102                (double)vrfToCoalescerBusWidth);
103
104    numCyclesPerLoadTransfer = (wfSize() * sizeof(uint32_t))
105                               / coalescerToVrfBusWidth;
106
107    lastVaddrWF.resize(numSIMDs);
108    wfList.resize(numSIMDs);
109
110    for (int j = 0; j < numSIMDs; ++j) {
111        lastVaddrWF[j].resize(p->n_wf);
112
113        for (int i = 0; i < p->n_wf; ++i) {
114            lastVaddrWF[j][i].resize(wfSize());
115
116            wfList[j].push_back(p->wavefronts[j * p->n_wf + i]);
117            wfList[j][i]->setParent(this);
118
119            for (int k = 0; k < wfSize(); ++k) {
120                lastVaddrWF[j][i][k] = 0;
121            }
122        }
123    }
124
125    lastVaddrSimd.resize(numSIMDs);
126
127    for (int i = 0; i < numSIMDs; ++i) {
128        lastVaddrSimd[i].resize(wfSize(), 0);
129    }
130
131    lastVaddrCU.resize(wfSize());
132
133    lds.setParent(this);
134
135    if (p->execPolicy == "OLDEST-FIRST") {
136        exec_policy = EXEC_POLICY::OLDEST;
137    } else if (p->execPolicy == "ROUND-ROBIN") {
138        exec_policy = EXEC_POLICY::RR;
139    } else {
140        fatal("Invalid WF execution policy (CU)\n");
141    }
142
143    memPort.resize(wfSize());
144
145    // resize the tlbPort vectorArray
146    int tlbPort_width = perLaneTLB ? wfSize() : 1;
147    tlbPort.resize(tlbPort_width);
148
149    cuExitCallback = new CUExitCallback(this);
150    registerExitCallback(cuExitCallback);
151
152    xactCasLoadMap.clear();
153    lastExecCycle.resize(numSIMDs, 0);
154
155    for (int i = 0; i < vrf.size(); ++i) {
156        vrf[i]->setParent(this);
157    }
158
159    numVecRegsPerSimd = vrf[0]->numRegs();
160}
161
162ComputeUnit::~ComputeUnit()
163{
164    // Delete wavefront slots
165    for (int j = 0; j < numSIMDs; ++j) {
166        for (int i = 0; i < shader->n_wf; ++i) {
167            delete wfList[j][i];
168        }
169        lastVaddrSimd[j].clear();
170    }
171    lastVaddrCU.clear();
172    readyList.clear();
173    waveStatusList.clear();
174    dispatchList.clear();
175    vectorAluInstAvail.clear();
176    delete cuExitCallback;
177    delete ldsPort;
178}
179
180void
181ComputeUnit::fillKernelState(Wavefront *w, NDRange *ndr)
182{
183    w->resizeRegFiles(ndr->q.cRegCount, ndr->q.sRegCount, ndr->q.dRegCount);
184
185    w->workGroupSz[0] = ndr->q.wgSize[0];
186    w->workGroupSz[1] = ndr->q.wgSize[1];
187    w->workGroupSz[2] = ndr->q.wgSize[2];
188    w->wgSz = w->workGroupSz[0] * w->workGroupSz[1] * w->workGroupSz[2];
189    w->gridSz[0] = ndr->q.gdSize[0];
190    w->gridSz[1] = ndr->q.gdSize[1];
191    w->gridSz[2] = ndr->q.gdSize[2];
192    w->kernelArgs = ndr->q.args;
193    w->privSizePerItem = ndr->q.privMemPerItem;
194    w->spillSizePerItem = ndr->q.spillMemPerItem;
195    w->roBase = ndr->q.roMemStart;
196    w->roSize = ndr->q.roMemTotal;
197    w->computeActualWgSz(ndr);
198}
199
200void
201ComputeUnit::updateEvents() {
202
203    if (!timestampVec.empty()) {
204        uint32_t vecSize = timestampVec.size();
205        uint32_t i = 0;
206        while (i < vecSize) {
207            if (timestampVec[i] <= shader->tick_cnt) {
208                std::pair<uint32_t, uint32_t> regInfo = regIdxVec[i];
209                vrf[regInfo.first]->markReg(regInfo.second, sizeof(uint32_t),
210                                            statusVec[i]);
211                timestampVec.erase(timestampVec.begin() + i);
212                regIdxVec.erase(regIdxVec.begin() + i);
213                statusVec.erase(statusVec.begin() + i);
214                --vecSize;
215                --i;
216            }
217            ++i;
218        }
219    }
220
221    for (int i = 0; i< numSIMDs; ++i) {
222        vrf[i]->updateEvents();
223    }
224}
225
226
227void
228ComputeUnit::startWavefront(Wavefront *w, int waveId, LdsChunk *ldsChunk,
229                            NDRange *ndr)
230{
231    static int _n_wave = 0;
232
233    VectorMask init_mask;
234    init_mask.reset();
235
236    for (int k = 0; k < wfSize(); ++k) {
237        if (k + waveId * wfSize() < w->actualWgSzTotal)
238            init_mask[k] = 1;
239    }
240
241    w->kernId = ndr->dispatchId;
242    w->wfId = waveId;
243    w->initMask = init_mask.to_ullong();
244
245    for (int k = 0; k < wfSize(); ++k) {
246        w->workItemId[0][k] = (k + waveId * wfSize()) % w->actualWgSz[0];
247        w->workItemId[1][k] = ((k + waveId * wfSize()) / w->actualWgSz[0]) %
248                             w->actualWgSz[1];
249        w->workItemId[2][k] = (k + waveId * wfSize()) /
250                              (w->actualWgSz[0] * w->actualWgSz[1]);
251
252        w->workItemFlatId[k] = w->workItemId[2][k] * w->actualWgSz[0] *
253            w->actualWgSz[1] + w->workItemId[1][k] * w->actualWgSz[0] +
254            w->workItemId[0][k];
255    }
256
257    w->barrierSlots = divCeil(w->actualWgSzTotal, wfSize());
258
259    w->barCnt.resize(wfSize(), 0);
260
261    w->maxBarCnt = 0;
262    w->oldBarrierCnt = 0;
263    w->barrierCnt = 0;
264
265    w->privBase = ndr->q.privMemStart;
266    ndr->q.privMemStart += ndr->q.privMemPerItem * wfSize();
267
268    w->spillBase = ndr->q.spillMemStart;
269    ndr->q.spillMemStart += ndr->q.spillMemPerItem * wfSize();
270
271    w->pushToReconvergenceStack(0, UINT32_MAX, init_mask.to_ulong());
272
273    // WG state
274    w->wgId = ndr->globalWgId;
275    w->dispatchId = ndr->dispatchId;
276    w->workGroupId[0] = w->wgId % ndr->numWg[0];
277    w->workGroupId[1] = (w->wgId / ndr->numWg[0]) % ndr->numWg[1];
278    w->workGroupId[2] = w->wgId / (ndr->numWg[0] * ndr->numWg[1]);
279
280    w->barrierId = barrier_id;
281    w->stalledAtBarrier = false;
282
283    // set the wavefront context to have a pointer to this section of the LDS
284    w->ldsChunk = ldsChunk;
285
286    int32_t refCount M5_VAR_USED =
287                    lds.increaseRefCounter(w->dispatchId, w->wgId);
288    DPRINTF(GPUDisp, "CU%d: increase ref ctr wg[%d] to [%d]\n",
289                    cu_id, w->wgId, refCount);
290
291    w->instructionBuffer.clear();
292
293    if (w->pendingFetch)
294        w->dropFetch = true;
295
296    // is this the last wavefront in the workgroup
297    // if set the spillWidth to be the remaining work-items
298    // so that the vector access is correct
299    if ((waveId + 1) * wfSize() >= w->actualWgSzTotal) {
300        w->spillWidth = w->actualWgSzTotal - (waveId * wfSize());
301    } else {
302        w->spillWidth = wfSize();
303    }
304
305    DPRINTF(GPUDisp, "Scheduling wfDynId/barrier_id %d/%d on CU%d: "
306            "WF[%d][%d]\n", _n_wave, barrier_id, cu_id, w->simdId, w->wfSlotId);
307
308    w->start(++_n_wave, ndr->q.code_ptr);
309}
310
311void
312ComputeUnit::StartWorkgroup(NDRange *ndr)
313{
314    // reserve the LDS capacity allocated to the work group
315    // disambiguated by the dispatch ID and workgroup ID, which should be
316    // globally unique
317    LdsChunk *ldsChunk = lds.reserveSpace(ndr->dispatchId, ndr->globalWgId,
318                                          ndr->q.ldsSize);
319
320    // Send L1 cache acquire
321    // isKernel + isAcquire = Kernel Begin
322    if (shader->impl_kern_boundary_sync) {
323        GPUDynInstPtr gpuDynInst =
324            std::make_shared<GPUDynInst>(this, nullptr, kernelLaunchInst,
325                                         getAndIncSeqNum());
326
327        gpuDynInst->useContinuation = false;
328        injectGlobalMemFence(gpuDynInst, true);
329    }
330
331    // calculate the number of 32-bit vector registers required by wavefront
332    int vregDemand = ndr->q.sRegCount + (2 * ndr->q.dRegCount);
333    int wave_id = 0;
334
335    // Assign WFs by spreading them across SIMDs, 1 WF per SIMD at a time
336    for (int m = 0; m < shader->n_wf * numSIMDs; ++m) {
337        Wavefront *w = wfList[m % numSIMDs][m / numSIMDs];
338        // Check if this wavefront slot is available:
339        // It must be stopped and not waiting
340        // for a release to complete S_RETURNING
341        if (w->status == Wavefront::S_STOPPED) {
342            fillKernelState(w, ndr);
343            // if we have scheduled all work items then stop
344            // scheduling wavefronts
345            if (wave_id * wfSize() >= w->actualWgSzTotal)
346                break;
347
348            // reserve vector registers for the scheduled wavefront
349            assert(vectorRegsReserved[m % numSIMDs] <= numVecRegsPerSimd);
350            uint32_t normSize = 0;
351
352            w->startVgprIndex = vrf[m % numSIMDs]->manager->
353                                    allocateRegion(vregDemand, &normSize);
354
355            w->reservedVectorRegs = normSize;
356            vectorRegsReserved[m % numSIMDs] += w->reservedVectorRegs;
357
358            startWavefront(w, wave_id, ldsChunk, ndr);
359            ++wave_id;
360        }
361    }
362    ++barrier_id;
363}
364
365int
366ComputeUnit::ReadyWorkgroup(NDRange *ndr)
367{
368    // Get true size of workgroup (after clamping to grid size)
369    int trueWgSize[3];
370    int trueWgSizeTotal = 1;
371
372    for (int d = 0; d < 3; ++d) {
373        trueWgSize[d] = std::min(ndr->q.wgSize[d], ndr->q.gdSize[d] -
374                                 ndr->wgId[d] * ndr->q.wgSize[d]);
375
376        trueWgSizeTotal *= trueWgSize[d];
377        DPRINTF(GPUDisp, "trueWgSize[%d] =  %d\n", d, trueWgSize[d]);
378    }
379
380    DPRINTF(GPUDisp, "trueWgSizeTotal =  %d\n", trueWgSizeTotal);
381
382    // calculate the number of 32-bit vector registers required by each
383    // work item of the work group
384    int vregDemandPerWI = ndr->q.sRegCount + (2 * ndr->q.dRegCount);
385    bool vregAvail = true;
386    int numWfs = (trueWgSizeTotal + wfSize() - 1) / wfSize();
387    int freeWfSlots = 0;
388    // check if the total number of VGPRs required by all WFs of the WG
389    // fit in the VRFs of all SIMD units
390    assert((numWfs * vregDemandPerWI) <= (numSIMDs * numVecRegsPerSimd));
391    int numMappedWfs = 0;
392    std::vector<int> numWfsPerSimd;
393    numWfsPerSimd.resize(numSIMDs, 0);
394    // find how many free WF slots we have across all SIMDs
395    for (int j = 0; j < shader->n_wf; ++j) {
396        for (int i = 0; i < numSIMDs; ++i) {
397            if (wfList[i][j]->status == Wavefront::S_STOPPED) {
398                // count the number of free WF slots
399                ++freeWfSlots;
400                if (numMappedWfs < numWfs) {
401                    // count the WFs to be assigned per SIMD
402                    numWfsPerSimd[i]++;
403                }
404                numMappedWfs++;
405            }
406        }
407    }
408
409    // if there are enough free WF slots then find if there are enough
410    // free VGPRs per SIMD based on the WF->SIMD mapping
411    if (freeWfSlots >= numWfs) {
412        for (int j = 0; j < numSIMDs; ++j) {
413            // find if there are enough free VGPR regions in the SIMD's VRF
414            // to accommodate the WFs of the new WG that would be mapped to
415            // this SIMD unit
416            vregAvail = vrf[j]->manager->canAllocate(numWfsPerSimd[j],
417                                                     vregDemandPerWI);
418
419            // stop searching if there is at least one SIMD
420            // whose VRF does not have enough free VGPR pools.
421            // This is because a WG is scheduled only if ALL
422            // of its WFs can be scheduled
423            if (!vregAvail)
424                break;
425        }
426    }
427
428    DPRINTF(GPUDisp, "Free WF slots =  %d, VGPR Availability = %d\n",
429            freeWfSlots, vregAvail);
430
431    if (!vregAvail) {
432        ++numTimesWgBlockedDueVgprAlloc;
433    }
434
435    // Return true if enough WF slots to submit workgroup and if there are
436    // enough VGPRs to schedule all WFs to their SIMD units
437    if (!lds.canReserve(ndr->q.ldsSize)) {
438        wgBlockedDueLdsAllocation++;
439    }
440
441    // Return true if (a) there are enough free WF slots to submit
442    // workgrounp and (b) if there are enough VGPRs to schedule all WFs to their
443    // SIMD units and (c) if there is enough space in LDS
444    return freeWfSlots >= numWfs && vregAvail && lds.canReserve(ndr->q.ldsSize);
445}
446
447int
448ComputeUnit::AllAtBarrier(uint32_t _barrier_id, uint32_t bcnt, uint32_t bslots)
449{
450    DPRINTF(GPUSync, "CU%d: Checking for All At Barrier\n", cu_id);
451    int ccnt = 0;
452
453    for (int i_simd = 0; i_simd < numSIMDs; ++i_simd) {
454        for (int i_wf = 0; i_wf < shader->n_wf; ++i_wf) {
455            Wavefront *w = wfList[i_simd][i_wf];
456
457            if (w->status == Wavefront::S_RUNNING) {
458                DPRINTF(GPUSync, "Checking WF[%d][%d]\n", i_simd, i_wf);
459
460                DPRINTF(GPUSync, "wf->barrier_id = %d, _barrier_id = %d\n",
461                        w->barrierId, _barrier_id);
462
463                DPRINTF(GPUSync, "wf->barrier_cnt %d, bcnt = %d\n",
464                        w->barrierCnt, bcnt);
465            }
466
467            if (w->status == Wavefront::S_RUNNING &&
468                w->barrierId == _barrier_id && w->barrierCnt == bcnt &&
469                !w->outstandingReqs) {
470                ++ccnt;
471
472                DPRINTF(GPUSync, "WF[%d][%d] at barrier, increment ccnt to "
473                        "%d\n", i_simd, i_wf, ccnt);
474            }
475        }
476    }
477
478    DPRINTF(GPUSync, "CU%d: returning allAtBarrier ccnt = %d, bslots = %d\n",
479            cu_id, ccnt, bslots);
480
481    return ccnt == bslots;
482}
483
484//  Check if the current wavefront is blocked on additional resources.
485bool
486ComputeUnit::cedeSIMD(int simdId, int wfSlotId)
487{
488    bool cede = false;
489
490    // If --xact-cas-mode option is enabled in run.py, then xact_cas_ld
491    // magic instructions will impact the scheduling of wavefronts
492    if (xact_cas_mode) {
493        /*
494         * When a wavefront calls xact_cas_ld, it adds itself to a per address
495         * queue. All per address queues are managed by the xactCasLoadMap.
496         *
497         * A wavefront is not blocked if: it is not in ANY per address queue or
498         * if it is at the head of a per address queue.
499         */
500        for (auto itMap : xactCasLoadMap) {
501            std::list<waveIdentifier> curWaveIDQueue = itMap.second.waveIDQueue;
502
503            if (!curWaveIDQueue.empty()) {
504                for (auto it : curWaveIDQueue) {
505                    waveIdentifier cur_wave = it;
506
507                    if (cur_wave.simdId == simdId &&
508                        cur_wave.wfSlotId == wfSlotId) {
509                        // 2 possibilities
510                        // 1: this WF has a green light
511                        // 2: another WF has a green light
512                        waveIdentifier owner_wave = curWaveIDQueue.front();
513
514                        if (owner_wave.simdId != cur_wave.simdId ||
515                            owner_wave.wfSlotId != cur_wave.wfSlotId) {
516                            // possibility 2
517                            cede = true;
518                            break;
519                        } else {
520                            // possibility 1
521                            break;
522                        }
523                    }
524                }
525            }
526        }
527    }
528
529    return cede;
530}
531
532// Execute one clock worth of work on the ComputeUnit.
533void
534ComputeUnit::exec()
535{
536    updateEvents();
537    // Execute pipeline stages in reverse order to simulate
538    // the pipeline latency
539    globalMemoryPipe.exec();
540    localMemoryPipe.exec();
541    execStage.exec();
542    scheduleStage.exec();
543    scoreboardCheckStage.exec();
544    fetchStage.exec();
545
546    totalCycles++;
547}
548
549void
550ComputeUnit::init()
551{
552    // Initialize CU Bus models
553    glbMemToVrfBus.init(&shader->tick_cnt, shader->ticks(1));
554    locMemToVrfBus.init(&shader->tick_cnt, shader->ticks(1));
555    nextGlbMemBus = 0;
556    nextLocMemBus = 0;
557    fatal_if(numGlbMemUnits > 1,
558             "No support for multiple Global Memory Pipelines exists!!!");
559    vrfToGlobalMemPipeBus.resize(numGlbMemUnits);
560    for (int j = 0; j < numGlbMemUnits; ++j) {
561        vrfToGlobalMemPipeBus[j] = WaitClass();
562        vrfToGlobalMemPipeBus[j].init(&shader->tick_cnt, shader->ticks(1));
563    }
564
565    fatal_if(numLocMemUnits > 1,
566             "No support for multiple Local Memory Pipelines exists!!!");
567    vrfToLocalMemPipeBus.resize(numLocMemUnits);
568    for (int j = 0; j < numLocMemUnits; ++j) {
569        vrfToLocalMemPipeBus[j] = WaitClass();
570        vrfToLocalMemPipeBus[j].init(&shader->tick_cnt, shader->ticks(1));
571    }
572    vectorRegsReserved.resize(numSIMDs, 0);
573    aluPipe.resize(numSIMDs);
574    wfWait.resize(numSIMDs + numLocMemUnits + numGlbMemUnits);
575
576    for (int i = 0; i < numSIMDs + numLocMemUnits + numGlbMemUnits; ++i) {
577        wfWait[i] = WaitClass();
578        wfWait[i].init(&shader->tick_cnt, shader->ticks(1));
579    }
580
581    for (int i = 0; i < numSIMDs; ++i) {
582        aluPipe[i] = WaitClass();
583        aluPipe[i].init(&shader->tick_cnt, shader->ticks(1));
584    }
585
586    // Setup space for call args
587    for (int j = 0; j < numSIMDs; ++j) {
588        for (int i = 0; i < shader->n_wf; ++i) {
589            wfList[j][i]->initCallArgMem(shader->funcargs_size, wavefrontSize);
590        }
591    }
592
593    // Initializing pipeline resources
594    readyList.resize(numSIMDs + numGlbMemUnits + numLocMemUnits);
595    waveStatusList.resize(numSIMDs);
596
597    for (int j = 0; j < numSIMDs; ++j) {
598        for (int i = 0; i < shader->n_wf; ++i) {
599            waveStatusList[j].push_back(
600                std::make_pair(wfList[j][i], BLOCKED));
601        }
602    }
603
604    for (int j = 0; j < (numSIMDs + numGlbMemUnits + numLocMemUnits); ++j) {
605        dispatchList.push_back(std::make_pair((Wavefront*)nullptr, EMPTY));
606    }
607
608    fetchStage.init(this);
609    scoreboardCheckStage.init(this);
610    scheduleStage.init(this);
611    execStage.init(this);
612    globalMemoryPipe.init(this);
613    localMemoryPipe.init(this);
614    // initialize state for statistics calculation
615    vectorAluInstAvail.resize(numSIMDs, false);
616    shrMemInstAvail = 0;
617    glbMemInstAvail = 0;
618}
619
620bool
621ComputeUnit::DataPort::recvTimingResp(PacketPtr pkt)
622{
623    // Ruby has completed the memory op. Schedule the mem_resp_event at the
624    // appropriate cycle to process the timing memory response
625    // This delay represents the pipeline delay
626    SenderState *sender_state = safe_cast<SenderState*>(pkt->senderState);
627    int index = sender_state->port_index;
628    GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst;
629
630    // Is the packet returned a Kernel End or Barrier
631    if (pkt->req->isKernel() && pkt->req->isRelease()) {
632        Wavefront *w =
633            computeUnit->wfList[gpuDynInst->simdId][gpuDynInst->wfSlotId];
634
635        // Check if we are waiting on Kernel End Release
636        if (w->status == Wavefront::S_RETURNING) {
637            DPRINTF(GPUDisp, "CU%d: WF[%d][%d][wv=%d]: WG id completed %d\n",
638                    computeUnit->cu_id, w->simdId, w->wfSlotId,
639                    w->wfDynId, w->kernId);
640
641            computeUnit->shader->dispatcher->notifyWgCompl(w);
642            w->status = Wavefront::S_STOPPED;
643        } else {
644            w->outstandingReqs--;
645        }
646
647        DPRINTF(GPUSync, "CU%d: WF[%d][%d]: barrier_cnt = %d\n",
648                computeUnit->cu_id, gpuDynInst->simdId,
649                gpuDynInst->wfSlotId, w->barrierCnt);
650
651        if (gpuDynInst->useContinuation) {
652            assert(!gpuDynInst->isNoScope());
653            gpuDynInst->execContinuation(gpuDynInst->staticInstruction(),
654                                           gpuDynInst);
655        }
656
657        delete pkt->senderState;
658        delete pkt->req;
659        delete pkt;
660        return true;
661    } else if (pkt->req->isKernel() && pkt->req->isAcquire()) {
662        if (gpuDynInst->useContinuation) {
663            assert(!gpuDynInst->isNoScope());
664            gpuDynInst->execContinuation(gpuDynInst->staticInstruction(),
665                                           gpuDynInst);
666        }
667
668        delete pkt->senderState;
669        delete pkt->req;
670        delete pkt;
671        return true;
672    }
673
674    EventFunctionWrapper *mem_resp_event =
675        computeUnit->memPort[index]->createMemRespEvent(pkt);
676
677    DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x received!\n",
678            computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
679            index, pkt->req->getPaddr());
680
681    computeUnit->schedule(mem_resp_event,
682                          curTick() + computeUnit->resp_tick_latency);
683    return true;
684}
685
686void
687ComputeUnit::DataPort::recvReqRetry()
688{
689    int len = retries.size();
690
691    assert(len > 0);
692
693    for (int i = 0; i < len; ++i) {
694        PacketPtr pkt = retries.front().first;
695        GPUDynInstPtr gpuDynInst M5_VAR_USED = retries.front().second;
696        DPRINTF(GPUMem, "CU%d: WF[%d][%d]: retry mem inst addr %#x\n",
697                computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
698                pkt->req->getPaddr());
699
700        /** Currently Ruby can return false due to conflicts for the particular
701         *  cache block or address.  Thus other requests should be allowed to
702         *  pass and the data port should expect multiple retries. */
703        if (!sendTimingReq(pkt)) {
704            DPRINTF(GPUMem, "failed again!\n");
705            break;
706        } else {
707            DPRINTF(GPUMem, "successful!\n");
708            retries.pop_front();
709        }
710    }
711}
712
713bool
714ComputeUnit::SQCPort::recvTimingResp(PacketPtr pkt)
715{
716    computeUnit->fetchStage.processFetchReturn(pkt);
717
718    return true;
719}
720
721void
722ComputeUnit::SQCPort::recvReqRetry()
723{
724    int len = retries.size();
725
726    assert(len > 0);
727
728    for (int i = 0; i < len; ++i) {
729        PacketPtr pkt = retries.front().first;
730        Wavefront *wavefront M5_VAR_USED = retries.front().second;
731        DPRINTF(GPUFetch, "CU%d: WF[%d][%d]: retrying FETCH addr %#x\n",
732                computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId,
733                pkt->req->getPaddr());
734        if (!sendTimingReq(pkt)) {
735            DPRINTF(GPUFetch, "failed again!\n");
736            break;
737        } else {
738            DPRINTF(GPUFetch, "successful!\n");
739            retries.pop_front();
740        }
741    }
742}
743
744void
745ComputeUnit::sendRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt)
746{
747    // There must be a way around this check to do the globalMemStart...
748    Addr tmp_vaddr = pkt->req->getVaddr();
749
750    updatePageDivergenceDist(tmp_vaddr);
751
752    pkt->req->setVirt(pkt->req->getAsid(), tmp_vaddr, pkt->req->getSize(),
753                      pkt->req->getFlags(), pkt->req->masterId(),
754                      pkt->req->getPC());
755
756    // figure out the type of the request to set read/write
757    BaseTLB::Mode TLB_mode;
758    assert(pkt->isRead() || pkt->isWrite());
759
760    // Check write before read for atomic operations
761    // since atomic operations should use BaseTLB::Write
762    if (pkt->isWrite()){
763        TLB_mode = BaseTLB::Write;
764    } else if (pkt->isRead()) {
765        TLB_mode = BaseTLB::Read;
766    } else {
767        fatal("pkt is not a read nor a write\n");
768    }
769
770    tlbCycles -= curTick();
771    ++tlbRequests;
772
773    int tlbPort_index = perLaneTLB ? index : 0;
774
775    if (shader->timingSim) {
776        if (debugSegFault) {
777            Process *p = shader->gpuTc->getProcessPtr();
778            Addr vaddr = pkt->req->getVaddr();
779            unsigned size = pkt->getSize();
780
781            if ((vaddr + size - 1) % 64 < vaddr % 64) {
782                panic("CU%d: WF[%d][%d]: Access to addr %#x is unaligned!\n",
783                      cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, vaddr);
784            }
785
786            Addr paddr;
787
788            if (!p->pTable->translate(vaddr, paddr)) {
789                if (!p->fixupStackFault(vaddr)) {
790                    panic("CU%d: WF[%d][%d]: Fault on addr %#x!\n",
791                          cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
792                          vaddr);
793                }
794            }
795        }
796
797        // This is the SenderState needed upon return
798        pkt->senderState = new DTLBPort::SenderState(gpuDynInst, index);
799
800        // This is the senderState needed by the TLB hierarchy to function
801        TheISA::GpuTLB::TranslationState *translation_state =
802          new TheISA::GpuTLB::TranslationState(TLB_mode, shader->gpuTc, false,
803                                               pkt->senderState);
804
805        pkt->senderState = translation_state;
806
807        if (functionalTLB) {
808            tlbPort[tlbPort_index]->sendFunctional(pkt);
809
810            // update the hitLevel distribution
811            int hit_level = translation_state->hitLevel;
812            assert(hit_level != -1);
813            hitsPerTLBLevel[hit_level]++;
814
815            // New SenderState for the memory access
816            X86ISA::GpuTLB::TranslationState *sender_state =
817                safe_cast<X86ISA::GpuTLB::TranslationState*>(pkt->senderState);
818
819            delete sender_state->tlbEntry;
820            delete sender_state->saved;
821            delete sender_state;
822
823            assert(pkt->req->hasPaddr());
824            assert(pkt->req->hasSize());
825
826            uint8_t *tmpData = pkt->getPtr<uint8_t>();
827
828            // this is necessary because the GPU TLB receives packets instead
829            // of requests. when the translation is complete, all relevent
830            // fields in the request will be populated, but not in the packet.
831            // here we create the new packet so we can set the size, addr,
832            // and proper flags.
833            PacketPtr oldPkt = pkt;
834            pkt = new Packet(oldPkt->req, oldPkt->cmd);
835            delete oldPkt;
836            pkt->dataStatic(tmpData);
837
838
839            // New SenderState for the memory access
840            pkt->senderState = new ComputeUnit::DataPort::SenderState(gpuDynInst,
841                                                             index, nullptr);
842
843            gpuDynInst->memStatusVector[pkt->getAddr()].push_back(index);
844            gpuDynInst->tlbHitLevel[index] = hit_level;
845
846
847            // translation is done. Schedule the mem_req_event at the
848            // appropriate cycle to send the timing memory request to ruby
849            EventFunctionWrapper *mem_req_event =
850                memPort[index]->createMemReqEvent(pkt);
851
852            DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x data "
853                    "scheduled\n", cu_id, gpuDynInst->simdId,
854                    gpuDynInst->wfSlotId, index, pkt->req->getPaddr());
855
856            schedule(mem_req_event, curTick() + req_tick_latency);
857        } else if (tlbPort[tlbPort_index]->isStalled()) {
858            assert(tlbPort[tlbPort_index]->retries.size() > 0);
859
860            DPRINTF(GPUTLB, "CU%d: WF[%d][%d]: Translation for addr %#x "
861                    "failed!\n", cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
862                    tmp_vaddr);
863
864            tlbPort[tlbPort_index]->retries.push_back(pkt);
865        } else if (!tlbPort[tlbPort_index]->sendTimingReq(pkt)) {
866            // Stall the data port;
867            // No more packet will be issued till
868            // ruby indicates resources are freed by
869            // a recvReqRetry() call back on this port.
870            tlbPort[tlbPort_index]->stallPort();
871
872            DPRINTF(GPUTLB, "CU%d: WF[%d][%d]: Translation for addr %#x "
873                    "failed!\n", cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
874                    tmp_vaddr);
875
876            tlbPort[tlbPort_index]->retries.push_back(pkt);
877        } else {
878           DPRINTF(GPUTLB,
879                   "CU%d: WF[%d][%d]: Translation for addr %#x sent!\n",
880                   cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, tmp_vaddr);
881        }
882    } else {
883        if (pkt->cmd == MemCmd::MemFenceReq) {
884            gpuDynInst->statusBitVector = VectorMask(0);
885        } else {
886            gpuDynInst->statusBitVector &= (~(1ll << index));
887        }
888
889        // New SenderState for the memory access
890        delete pkt->senderState;
891
892        // Because it's atomic operation, only need TLB translation state
893        pkt->senderState = new TheISA::GpuTLB::TranslationState(TLB_mode,
894                                                                shader->gpuTc);
895
896        tlbPort[tlbPort_index]->sendFunctional(pkt);
897
898        // the addr of the packet is not modified, so we need to create a new
899        // packet, or otherwise the memory access will have the old virtual
900        // address sent in the translation packet, instead of the physical
901        // address returned by the translation.
902        PacketPtr new_pkt = new Packet(pkt->req, pkt->cmd);
903        new_pkt->dataStatic(pkt->getPtr<uint8_t>());
904
905        // Translation is done. It is safe to send the packet to memory.
906        memPort[0]->sendFunctional(new_pkt);
907
908        DPRINTF(GPUMem, "CU%d: WF[%d][%d]: index %d: addr %#x\n", cu_id,
909                gpuDynInst->simdId, gpuDynInst->wfSlotId, index,
910                new_pkt->req->getPaddr());
911
912        // safe_cast the senderState
913        TheISA::GpuTLB::TranslationState *sender_state =
914             safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
915
916        delete sender_state->tlbEntry;
917        delete new_pkt;
918        delete pkt->senderState;
919        delete pkt->req;
920        delete pkt;
921    }
922}
923
924void
925ComputeUnit::sendSyncRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt)
926{
927    EventFunctionWrapper *mem_req_event =
928        memPort[index]->createMemReqEvent(pkt);
929
930
931    // New SenderState for the memory access
932    pkt->senderState = new ComputeUnit::DataPort::SenderState(gpuDynInst, index,
933                                                              nullptr);
934
935    DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x sync scheduled\n",
936            cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, index,
937            pkt->req->getPaddr());
938
939    schedule(mem_req_event, curTick() + req_tick_latency);
940}
941
942void
943ComputeUnit::injectGlobalMemFence(GPUDynInstPtr gpuDynInst, bool kernelLaunch,
944                                  Request* req)
945{
946    assert(gpuDynInst->isGlobalSeg());
947
948    if (!req) {
949        req = new Request(0, 0, 0, 0, masterId(), 0, gpuDynInst->wfDynId);
950    }
951    req->setPaddr(0);
952    if (kernelLaunch) {
953        req->setFlags(Request::KERNEL);
954    }
955
956    // for non-kernel MemFence operations, memorder flags are set depending
957    // on which type of request is currently being sent, so this
958    // should be set by the caller (e.g. if an inst has acq-rel
959    // semantics, it will send one acquire req an one release req)
960    gpuDynInst->setRequestFlags(req, kernelLaunch);
961
962    // a mem fence must correspond to an acquire/release request
963    assert(req->isAcquire() || req->isRelease());
964
965    // create packet
966    PacketPtr pkt = new Packet(req, MemCmd::MemFenceReq);
967
968    // set packet's sender state
969    pkt->senderState =
970        new ComputeUnit::DataPort::SenderState(gpuDynInst, 0, nullptr);
971
972    // send the packet
973    sendSyncRequest(gpuDynInst, 0, pkt);
974}
975
976void
977ComputeUnit::DataPort::processMemRespEvent(PacketPtr pkt)
978{
979    DataPort::SenderState *sender_state =
980        safe_cast<DataPort::SenderState*>(pkt->senderState);
981
982    GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst;
983    ComputeUnit *compute_unit = computeUnit;
984
985    assert(gpuDynInst);
986
987    DPRINTF(GPUPort, "CU%d: WF[%d][%d]: Response for addr %#x, index %d\n",
988            compute_unit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
989            pkt->req->getPaddr(), index);
990
991    Addr paddr = pkt->req->getPaddr();
992
993    if (pkt->cmd != MemCmd::MemFenceResp) {
994        int index = gpuDynInst->memStatusVector[paddr].back();
995
996        DPRINTF(GPUMem, "Response for addr %#x, index %d\n",
997                pkt->req->getPaddr(), index);
998
999        gpuDynInst->memStatusVector[paddr].pop_back();
1000        gpuDynInst->pAddr = pkt->req->getPaddr();
1001
1002        if (pkt->isRead() || pkt->isWrite()) {
1003
1004            if (gpuDynInst->n_reg <= MAX_REGS_FOR_NON_VEC_MEM_INST) {
1005                gpuDynInst->statusBitVector &= (~(1ULL << index));
1006            } else {
1007                assert(gpuDynInst->statusVector[index] > 0);
1008                gpuDynInst->statusVector[index]--;
1009
1010                if (!gpuDynInst->statusVector[index])
1011                    gpuDynInst->statusBitVector &= (~(1ULL << index));
1012            }
1013
1014            DPRINTF(GPUMem, "bitvector is now %#x\n",
1015                    gpuDynInst->statusBitVector);
1016
1017            if (gpuDynInst->statusBitVector == VectorMask(0)) {
1018                auto iter = gpuDynInst->memStatusVector.begin();
1019                auto end = gpuDynInst->memStatusVector.end();
1020
1021                while (iter != end) {
1022                    assert(iter->second.empty());
1023                    ++iter;
1024                }
1025
1026                gpuDynInst->memStatusVector.clear();
1027
1028                if (gpuDynInst->n_reg > MAX_REGS_FOR_NON_VEC_MEM_INST)
1029                    gpuDynInst->statusVector.clear();
1030
1031                compute_unit->globalMemoryPipe.handleResponse(gpuDynInst);
1032
1033                DPRINTF(GPUMem, "CU%d: WF[%d][%d]: packet totally complete\n",
1034                        compute_unit->cu_id, gpuDynInst->simdId,
1035                        gpuDynInst->wfSlotId);
1036
1037                // after clearing the status vectors,
1038                // see if there is a continuation to perform
1039                // the continuation may generate more work for
1040                // this memory request
1041                if (gpuDynInst->useContinuation) {
1042                    assert(!gpuDynInst->isNoScope());
1043                    gpuDynInst->execContinuation(
1044                        gpuDynInst->staticInstruction(),
1045                        gpuDynInst);
1046                }
1047            }
1048        }
1049    } else {
1050        gpuDynInst->statusBitVector = VectorMask(0);
1051
1052        if (gpuDynInst->useContinuation) {
1053            assert(!gpuDynInst->isNoScope());
1054            gpuDynInst->execContinuation(gpuDynInst->staticInstruction(),
1055                                         gpuDynInst);
1056        }
1057    }
1058
1059    delete pkt->senderState;
1060    delete pkt->req;
1061    delete pkt;
1062}
1063
1064ComputeUnit*
1065ComputeUnitParams::create()
1066{
1067    return new ComputeUnit(this);
1068}
1069
1070bool
1071ComputeUnit::DTLBPort::recvTimingResp(PacketPtr pkt)
1072{
1073    Addr line = pkt->req->getPaddr();
1074
1075    DPRINTF(GPUTLB, "CU%d: DTLBPort received %#x->%#x\n", computeUnit->cu_id,
1076            pkt->req->getVaddr(), line);
1077
1078    assert(pkt->senderState);
1079    computeUnit->tlbCycles += curTick();
1080
1081    // pop off the TLB translation state
1082    TheISA::GpuTLB::TranslationState *translation_state =
1083               safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
1084
1085    // no PageFaults are permitted for data accesses
1086    if (!translation_state->tlbEntry) {
1087        DTLBPort::SenderState *sender_state =
1088            safe_cast<DTLBPort::SenderState*>(translation_state->saved);
1089
1090        Wavefront *w M5_VAR_USED =
1091            computeUnit->wfList[sender_state->_gpuDynInst->simdId]
1092            [sender_state->_gpuDynInst->wfSlotId];
1093
1094        DPRINTFN("Wave %d couldn't tranlate vaddr %#x\n", w->wfDynId,
1095                 pkt->req->getVaddr());
1096    }
1097
1098    // update the hitLevel distribution
1099    int hit_level = translation_state->hitLevel;
1100    computeUnit->hitsPerTLBLevel[hit_level]++;
1101
1102    delete translation_state->tlbEntry;
1103    assert(!translation_state->ports.size());
1104    pkt->senderState = translation_state->saved;
1105
1106    // for prefetch pkt
1107    BaseTLB::Mode TLB_mode = translation_state->tlbMode;
1108
1109    delete translation_state;
1110
1111    // use the original sender state to know how to close this transaction
1112    DTLBPort::SenderState *sender_state =
1113        safe_cast<DTLBPort::SenderState*>(pkt->senderState);
1114
1115    GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst;
1116    int mp_index = sender_state->portIndex;
1117    Addr vaddr = pkt->req->getVaddr();
1118    gpuDynInst->memStatusVector[line].push_back(mp_index);
1119    gpuDynInst->tlbHitLevel[mp_index] = hit_level;
1120
1121    MemCmd requestCmd;
1122
1123    if (pkt->cmd == MemCmd::ReadResp) {
1124        requestCmd = MemCmd::ReadReq;
1125    } else if (pkt->cmd == MemCmd::WriteResp) {
1126        requestCmd = MemCmd::WriteReq;
1127    } else if (pkt->cmd == MemCmd::SwapResp) {
1128        requestCmd = MemCmd::SwapReq;
1129    } else {
1130        panic("unsupported response to request conversion %s\n",
1131              pkt->cmd.toString());
1132    }
1133
1134    if (computeUnit->prefetchDepth) {
1135        int simdId = gpuDynInst->simdId;
1136        int wfSlotId = gpuDynInst->wfSlotId;
1137        Addr last = 0;
1138
1139        switch(computeUnit->prefetchType) {
1140        case Enums::PF_CU:
1141            last = computeUnit->lastVaddrCU[mp_index];
1142            break;
1143        case Enums::PF_PHASE:
1144            last = computeUnit->lastVaddrSimd[simdId][mp_index];
1145            break;
1146        case Enums::PF_WF:
1147            last = computeUnit->lastVaddrWF[simdId][wfSlotId][mp_index];
1148        default:
1149            break;
1150        }
1151
1152        DPRINTF(GPUPrefetch, "CU[%d][%d][%d][%d]: %#x was last\n",
1153                computeUnit->cu_id, simdId, wfSlotId, mp_index, last);
1154
1155        int stride = last ? (roundDown(vaddr, TheISA::PageBytes) -
1156                     roundDown(last, TheISA::PageBytes)) >> TheISA::PageShift
1157                     : 0;
1158
1159        DPRINTF(GPUPrefetch, "Stride is %d\n", stride);
1160
1161        computeUnit->lastVaddrCU[mp_index] = vaddr;
1162        computeUnit->lastVaddrSimd[simdId][mp_index] = vaddr;
1163        computeUnit->lastVaddrWF[simdId][wfSlotId][mp_index] = vaddr;
1164
1165        stride = (computeUnit->prefetchType == Enums::PF_STRIDE) ?
1166            computeUnit->prefetchStride: stride;
1167
1168        DPRINTF(GPUPrefetch, "%#x to: CU[%d][%d][%d][%d]\n", vaddr,
1169                computeUnit->cu_id, simdId, wfSlotId, mp_index);
1170
1171        DPRINTF(GPUPrefetch, "Prefetching from %#x:", vaddr);
1172
1173        // Prefetch Next few pages atomically
1174        for (int pf = 1; pf <= computeUnit->prefetchDepth; ++pf) {
1175            DPRINTF(GPUPrefetch, "%d * %d: %#x\n", pf, stride,
1176                    vaddr+stride*pf*TheISA::PageBytes);
1177
1178            if (!stride)
1179                break;
1180
1181            Request *prefetch_req = new Request(0, vaddr + stride * pf *
1182                                                TheISA::PageBytes,
1183                                                sizeof(uint8_t), 0,
1184                                                computeUnit->masterId(),
1185                                                0, 0, 0);
1186
1187            PacketPtr prefetch_pkt = new Packet(prefetch_req, requestCmd);
1188            uint8_t foo = 0;
1189            prefetch_pkt->dataStatic(&foo);
1190
1191            // Because it's atomic operation, only need TLB translation state
1192            prefetch_pkt->senderState =
1193                new TheISA::GpuTLB::TranslationState(TLB_mode,
1194                                                     computeUnit->shader->gpuTc,
1195                                                     true);
1196
1197            // Currently prefetches are zero-latency, hence the sendFunctional
1198            sendFunctional(prefetch_pkt);
1199
1200            /* safe_cast the senderState */
1201            TheISA::GpuTLB::TranslationState *tlb_state =
1202                 safe_cast<TheISA::GpuTLB::TranslationState*>(
1203                         prefetch_pkt->senderState);
1204
1205
1206            delete tlb_state->tlbEntry;
1207            delete tlb_state;
1208            delete prefetch_pkt->req;
1209            delete prefetch_pkt;
1210        }
1211    }
1212
1213    // First we must convert the response cmd back to a request cmd so that
1214    // the request can be sent through the cu's master port
1215    PacketPtr new_pkt = new Packet(pkt->req, requestCmd);
1216    new_pkt->dataStatic(pkt->getPtr<uint8_t>());
1217    delete pkt->senderState;
1218    delete pkt;
1219
1220    // New SenderState for the memory access
1221    new_pkt->senderState =
1222            new ComputeUnit::DataPort::SenderState(gpuDynInst, mp_index,
1223                                                   nullptr);
1224
1225    // translation is done. Schedule the mem_req_event at the appropriate
1226    // cycle to send the timing memory request to ruby
1227    EventFunctionWrapper *mem_req_event =
1228        computeUnit->memPort[mp_index]->createMemReqEvent(new_pkt);
1229
1230    DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x data scheduled\n",
1231            computeUnit->cu_id, gpuDynInst->simdId,
1232            gpuDynInst->wfSlotId, mp_index, new_pkt->req->getPaddr());
1233
1234    computeUnit->schedule(mem_req_event, curTick() +
1235                          computeUnit->req_tick_latency);
1236
1237    return true;
1238}
1239
1240EventFunctionWrapper*
1241ComputeUnit::DataPort::createMemReqEvent(PacketPtr pkt)
1242{
1243    return new EventFunctionWrapper(
1244        [this, pkt]{ processMemReqEvent(pkt); },
1245        "ComputeUnit memory request event", true);
1246}
1247
1248EventFunctionWrapper*
1249ComputeUnit::DataPort::createMemRespEvent(PacketPtr pkt)
1250{
1251    return new EventFunctionWrapper(
1252        [this, pkt]{ processMemRespEvent(pkt); },
1253        "ComputeUnit memory response event", true);
1254}
1255
1256void
1257ComputeUnit::DataPort::processMemReqEvent(PacketPtr pkt)
1258{
1259    SenderState *sender_state = safe_cast<SenderState*>(pkt->senderState);
1260    GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst;
1261    ComputeUnit *compute_unit M5_VAR_USED = computeUnit;
1262
1263    if (!(sendTimingReq(pkt))) {
1264        retries.push_back(std::make_pair(pkt, gpuDynInst));
1265
1266        DPRINTF(GPUPort,
1267                "CU%d: WF[%d][%d]: index %d, addr %#x data req failed!\n",
1268                compute_unit->cu_id, gpuDynInst->simdId,
1269                gpuDynInst->wfSlotId, index,
1270                pkt->req->getPaddr());
1271    } else {
1272        DPRINTF(GPUPort,
1273                "CU%d: WF[%d][%d]: index %d, addr %#x data req sent!\n",
1274                compute_unit->cu_id, gpuDynInst->simdId,
1275                gpuDynInst->wfSlotId, index,
1276                pkt->req->getPaddr());
1277    }
1278}
1279
1280/*
1281 * The initial translation request could have been rejected,
1282 * if <retries> queue is not Retry sending the translation
1283 * request. sendRetry() is called from the peer port whenever
1284 * a translation completes.
1285 */
1286void
1287ComputeUnit::DTLBPort::recvReqRetry()
1288{
1289    int len = retries.size();
1290
1291    DPRINTF(GPUTLB, "CU%d: DTLB recvReqRetry - %d pending requests\n",
1292            computeUnit->cu_id, len);
1293
1294    assert(len > 0);
1295    assert(isStalled());
1296    // recvReqRetry is an indication that the resource on which this
1297    // port was stalling on is freed. So, remove the stall first
1298    unstallPort();
1299
1300    for (int i = 0; i < len; ++i) {
1301        PacketPtr pkt = retries.front();
1302        Addr vaddr M5_VAR_USED = pkt->req->getVaddr();
1303        DPRINTF(GPUTLB, "CU%d: retrying D-translaton for address%#x", vaddr);
1304
1305        if (!sendTimingReq(pkt)) {
1306            // Stall port
1307            stallPort();
1308            DPRINTF(GPUTLB, ": failed again\n");
1309            break;
1310        } else {
1311            DPRINTF(GPUTLB, ": successful\n");
1312            retries.pop_front();
1313        }
1314    }
1315}
1316
1317bool
1318ComputeUnit::ITLBPort::recvTimingResp(PacketPtr pkt)
1319{
1320    Addr line M5_VAR_USED = pkt->req->getPaddr();
1321    DPRINTF(GPUTLB, "CU%d: ITLBPort received %#x->%#x\n",
1322            computeUnit->cu_id, pkt->req->getVaddr(), line);
1323
1324    assert(pkt->senderState);
1325
1326    // pop off the TLB translation state
1327    TheISA::GpuTLB::TranslationState *translation_state =
1328                 safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
1329
1330    bool success = translation_state->tlbEntry != nullptr;
1331    delete translation_state->tlbEntry;
1332    assert(!translation_state->ports.size());
1333    pkt->senderState = translation_state->saved;
1334    delete translation_state;
1335
1336    // use the original sender state to know how to close this transaction
1337    ITLBPort::SenderState *sender_state =
1338        safe_cast<ITLBPort::SenderState*>(pkt->senderState);
1339
1340    // get the wavefront associated with this translation request
1341    Wavefront *wavefront = sender_state->wavefront;
1342    delete pkt->senderState;
1343
1344    if (success) {
1345        // pkt is reused in fetch(), don't delete it here.  However, we must
1346        // reset the command to be a request so that it can be sent through
1347        // the cu's master port
1348        assert(pkt->cmd == MemCmd::ReadResp);
1349        pkt->cmd = MemCmd::ReadReq;
1350
1351        computeUnit->fetchStage.fetch(pkt, wavefront);
1352    } else {
1353        if (wavefront->dropFetch) {
1354            assert(wavefront->instructionBuffer.empty());
1355            wavefront->dropFetch = false;
1356        }
1357
1358        wavefront->pendingFetch = 0;
1359    }
1360
1361    return true;
1362}
1363
1364/*
1365 * The initial translation request could have been rejected, if
1366 * <retries> queue is not empty. Retry sending the translation
1367 * request. sendRetry() is called from the peer port whenever
1368 * a translation completes.
1369 */
1370void
1371ComputeUnit::ITLBPort::recvReqRetry()
1372{
1373
1374    int len = retries.size();
1375    DPRINTF(GPUTLB, "CU%d: ITLB recvReqRetry - %d pending requests\n", len);
1376
1377    assert(len > 0);
1378    assert(isStalled());
1379
1380    // recvReqRetry is an indication that the resource on which this
1381    // port was stalling on is freed. So, remove the stall first
1382    unstallPort();
1383
1384    for (int i = 0; i < len; ++i) {
1385        PacketPtr pkt = retries.front();
1386        Addr vaddr M5_VAR_USED = pkt->req->getVaddr();
1387        DPRINTF(GPUTLB, "CU%d: retrying I-translaton for address%#x", vaddr);
1388
1389        if (!sendTimingReq(pkt)) {
1390            stallPort(); // Stall port
1391            DPRINTF(GPUTLB, ": failed again\n");
1392            break;
1393        } else {
1394            DPRINTF(GPUTLB, ": successful\n");
1395            retries.pop_front();
1396        }
1397    }
1398}
1399
1400void
1401ComputeUnit::regStats()
1402{
1403    MemObject::regStats();
1404
1405    vALUInsts
1406        .name(name() + ".valu_insts")
1407        .desc("Number of vector ALU insts issued.")
1408        ;
1409    vALUInstsPerWF
1410        .name(name() + ".valu_insts_per_wf")
1411        .desc("The avg. number of vector ALU insts issued per-wavefront.")
1412        ;
1413    sALUInsts
1414        .name(name() + ".salu_insts")
1415        .desc("Number of scalar ALU insts issued.")
1416        ;
1417    sALUInstsPerWF
1418        .name(name() + ".salu_insts_per_wf")
1419        .desc("The avg. number of scalar ALU insts issued per-wavefront.")
1420        ;
1421    instCyclesVALU
1422        .name(name() + ".inst_cycles_valu")
1423        .desc("Number of cycles needed to execute VALU insts.")
1424        ;
1425    instCyclesSALU
1426        .name(name() + ".inst_cycles_salu")
1427        .desc("Number of cycles needed to execute SALU insts.")
1428        ;
1429    threadCyclesVALU
1430        .name(name() + ".thread_cycles_valu")
1431        .desc("Number of thread cycles used to execute vector ALU ops. "
1432              "Similar to instCyclesVALU but multiplied by the number of "
1433              "active threads.")
1434        ;
1435    vALUUtilization
1436        .name(name() + ".valu_utilization")
1437        .desc("Percentage of active vector ALU threads in a wave.")
1438        ;
1439    ldsNoFlatInsts
1440        .name(name() + ".lds_no_flat_insts")
1441        .desc("Number of LDS insts issued, not including FLAT "
1442              "accesses that resolve to LDS.")
1443        ;
1444    ldsNoFlatInstsPerWF
1445        .name(name() + ".lds_no_flat_insts_per_wf")
1446        .desc("The avg. number of LDS insts (not including FLAT "
1447              "accesses that resolve to LDS) per-wavefront.")
1448        ;
1449    flatVMemInsts
1450        .name(name() + ".flat_vmem_insts")
1451        .desc("The number of FLAT insts that resolve to vmem issued.")
1452        ;
1453    flatVMemInstsPerWF
1454        .name(name() + ".flat_vmem_insts_per_wf")
1455        .desc("The average number of FLAT insts that resolve to vmem "
1456              "issued per-wavefront.")
1457        ;
1458    flatLDSInsts
1459        .name(name() + ".flat_lds_insts")
1460        .desc("The number of FLAT insts that resolve to LDS issued.")
1461        ;
1462    flatLDSInstsPerWF
1463        .name(name() + ".flat_lds_insts_per_wf")
1464        .desc("The average number of FLAT insts that resolve to LDS "
1465              "issued per-wavefront.")
1466        ;
1467    vectorMemWrites
1468        .name(name() + ".vector_mem_writes")
1469        .desc("Number of vector mem write insts (excluding FLAT insts).")
1470        ;
1471    vectorMemWritesPerWF
1472        .name(name() + ".vector_mem_writes_per_wf")
1473        .desc("The average number of vector mem write insts "
1474              "(excluding FLAT insts) per-wavefront.")
1475        ;
1476    vectorMemReads
1477        .name(name() + ".vector_mem_reads")
1478        .desc("Number of vector mem read insts (excluding FLAT insts).")
1479        ;
1480    vectorMemReadsPerWF
1481        .name(name() + ".vector_mem_reads_per_wf")
1482        .desc("The avg. number of vector mem read insts (excluding "
1483              "FLAT insts) per-wavefront.")
1484        ;
1485    scalarMemWrites
1486        .name(name() + ".scalar_mem_writes")
1487        .desc("Number of scalar mem write insts.")
1488        ;
1489    scalarMemWritesPerWF
1490        .name(name() + ".scalar_mem_writes_per_wf")
1491        .desc("The average number of scalar mem write insts per-wavefront.")
1492        ;
1493    scalarMemReads
1494        .name(name() + ".scalar_mem_reads")
1495        .desc("Number of scalar mem read insts.")
1496        ;
1497    scalarMemReadsPerWF
1498        .name(name() + ".scalar_mem_reads_per_wf")
1499        .desc("The average number of scalar mem read insts per-wavefront.")
1500        ;
1501
1502    vALUInstsPerWF = vALUInsts / completedWfs;
1503    sALUInstsPerWF = sALUInsts / completedWfs;
1504    vALUUtilization = (threadCyclesVALU / (64 * instCyclesVALU)) * 100;
1505    ldsNoFlatInstsPerWF = ldsNoFlatInsts / completedWfs;
1506    flatVMemInstsPerWF = flatVMemInsts / completedWfs;
1507    flatLDSInstsPerWF = flatLDSInsts / completedWfs;
1508    vectorMemWritesPerWF = vectorMemWrites / completedWfs;
1509    vectorMemReadsPerWF = vectorMemReads / completedWfs;
1510    scalarMemWritesPerWF = scalarMemWrites / completedWfs;
1511    scalarMemReadsPerWF = scalarMemReads / completedWfs;
1512
1513    tlbCycles
1514        .name(name() + ".tlb_cycles")
1515        .desc("total number of cycles for all uncoalesced requests")
1516        ;
1517
1518    tlbRequests
1519        .name(name() + ".tlb_requests")
1520        .desc("number of uncoalesced requests")
1521        ;
1522
1523    tlbLatency
1524        .name(name() + ".avg_translation_latency")
1525        .desc("Avg. translation latency for data translations")
1526        ;
1527
1528    tlbLatency = tlbCycles / tlbRequests;
1529
1530    hitsPerTLBLevel
1531       .init(4)
1532       .name(name() + ".TLB_hits_distribution")
1533       .desc("TLB hits distribution (0 for page table, x for Lx-TLB")
1534       ;
1535
1536    // fixed number of TLB levels
1537    for (int i = 0; i < 4; ++i) {
1538        if (!i)
1539            hitsPerTLBLevel.subname(i,"page_table");
1540        else
1541            hitsPerTLBLevel.subname(i, csprintf("L%d_TLB",i));
1542    }
1543
1544    execRateDist
1545        .init(0, 10, 2)
1546        .name(name() + ".inst_exec_rate")
1547        .desc("Instruction Execution Rate: Number of executed vector "
1548              "instructions per cycle")
1549        ;
1550
1551    ldsBankConflictDist
1552       .init(0, wfSize(), 2)
1553       .name(name() + ".lds_bank_conflicts")
1554       .desc("Number of bank conflicts per LDS memory packet")
1555       ;
1556
1557    ldsBankAccesses
1558        .name(name() + ".lds_bank_access_cnt")
1559        .desc("Total number of LDS bank accesses")
1560        ;
1561
1562    pageDivergenceDist
1563        // A wavefront can touch up to N pages per memory instruction where
1564        // N is equal to the wavefront size
1565        // The number of pages per bin can be configured (here it's 4).
1566       .init(1, wfSize(), 4)
1567       .name(name() + ".page_divergence_dist")
1568       .desc("pages touched per wf (over all mem. instr.)")
1569       ;
1570
1571    controlFlowDivergenceDist
1572        .init(1, wfSize(), 4)
1573        .name(name() + ".warp_execution_dist")
1574        .desc("number of lanes active per instruction (oval all instructions)")
1575        ;
1576
1577    activeLanesPerGMemInstrDist
1578        .init(1, wfSize(), 4)
1579        .name(name() + ".gmem_lanes_execution_dist")
1580        .desc("number of active lanes per global memory instruction")
1581        ;
1582
1583    activeLanesPerLMemInstrDist
1584        .init(1, wfSize(), 4)
1585        .name(name() + ".lmem_lanes_execution_dist")
1586        .desc("number of active lanes per local memory instruction")
1587        ;
1588
1589    numInstrExecuted
1590        .name(name() + ".num_instr_executed")
1591        .desc("number of instructions executed")
1592        ;
1593
1594    numVecOpsExecuted
1595        .name(name() + ".num_vec_ops_executed")
1596        .desc("number of vec ops executed (e.g. WF size/inst)")
1597        ;
1598
1599    totalCycles
1600        .name(name() + ".num_total_cycles")
1601        .desc("number of cycles the CU ran for")
1602        ;
1603
1604    ipc
1605        .name(name() + ".ipc")
1606        .desc("Instructions per cycle (this CU only)")
1607        ;
1608
1609    vpc
1610        .name(name() + ".vpc")
1611        .desc("Vector Operations per cycle (this CU only)")
1612        ;
1613
1614    numALUInstsExecuted
1615        .name(name() + ".num_alu_insts_executed")
1616        .desc("Number of dynamic non-GM memory insts executed")
1617        ;
1618
1619    wgBlockedDueLdsAllocation
1620        .name(name() + ".wg_blocked_due_lds_alloc")
1621        .desc("Workgroup blocked due to LDS capacity")
1622        ;
1623
1624    ipc = numInstrExecuted / totalCycles;
1625    vpc = numVecOpsExecuted / totalCycles;
1626
1627    numTimesWgBlockedDueVgprAlloc
1628        .name(name() + ".times_wg_blocked_due_vgpr_alloc")
1629        .desc("Number of times WGs are blocked due to VGPR allocation per SIMD")
1630        ;
1631
1632    dynamicGMemInstrCnt
1633        .name(name() + ".global_mem_instr_cnt")
1634        .desc("dynamic global memory instructions count")
1635        ;
1636
1637    dynamicLMemInstrCnt
1638        .name(name() + ".local_mem_instr_cnt")
1639        .desc("dynamic local memory intruction count")
1640        ;
1641
1642    numALUInstsExecuted = numInstrExecuted - dynamicGMemInstrCnt -
1643        dynamicLMemInstrCnt;
1644
1645    completedWfs
1646        .name(name() + ".num_completed_wfs")
1647        .desc("number of completed wavefronts")
1648        ;
1649
1650    numCASOps
1651        .name(name() + ".num_CAS_ops")
1652        .desc("number of compare and swap operations")
1653        ;
1654
1655    numFailedCASOps
1656        .name(name() + ".num_failed_CAS_ops")
1657        .desc("number of compare and swap operations that failed")
1658        ;
1659
1660    // register stats of pipeline stages
1661    fetchStage.regStats();
1662    scoreboardCheckStage.regStats();
1663    scheduleStage.regStats();
1664    execStage.regStats();
1665
1666    // register stats of memory pipeline
1667    globalMemoryPipe.regStats();
1668    localMemoryPipe.regStats();
1669}
1670
1671void
1672ComputeUnit::updateInstStats(GPUDynInstPtr gpuDynInst)
1673{
1674    if (gpuDynInst->isScalar()) {
1675        if (gpuDynInst->isALU() && !gpuDynInst->isWaitcnt()) {
1676            sALUInsts++;
1677            instCyclesSALU++;
1678        } else if (gpuDynInst->isLoad()) {
1679            scalarMemReads++;
1680        } else if (gpuDynInst->isStore()) {
1681            scalarMemWrites++;
1682        }
1683    } else {
1684        if (gpuDynInst->isALU()) {
1685            vALUInsts++;
1686            instCyclesVALU++;
1687            threadCyclesVALU += gpuDynInst->wavefront()->execMask().count();
1688        } else if (gpuDynInst->isFlat()) {
1689            if (gpuDynInst->isLocalMem()) {
1690                flatLDSInsts++;
1691            } else {
1692                flatVMemInsts++;
1693            }
1694        } else if (gpuDynInst->isLocalMem()) {
1695            ldsNoFlatInsts++;
1696        } else if (gpuDynInst->isLoad()) {
1697            vectorMemReads++;
1698        } else if (gpuDynInst->isStore()) {
1699            vectorMemWrites++;
1700        }
1701    }
1702}
1703
1704void
1705ComputeUnit::updatePageDivergenceDist(Addr addr)
1706{
1707    Addr virt_page_addr = roundDown(addr, TheISA::PageBytes);
1708
1709    if (!pagesTouched.count(virt_page_addr))
1710        pagesTouched[virt_page_addr] = 1;
1711    else
1712        pagesTouched[virt_page_addr]++;
1713}
1714
1715void
1716ComputeUnit::CUExitCallback::process()
1717{
1718    if (computeUnit->countPages) {
1719        std::ostream *page_stat_file =
1720            simout.create(computeUnit->name().c_str())->stream();
1721
1722        *page_stat_file << "page, wavefront accesses, workitem accesses" <<
1723            std::endl;
1724
1725        for (auto iter : computeUnit->pageAccesses) {
1726            *page_stat_file << std::hex << iter.first << ",";
1727            *page_stat_file << std::dec << iter.second.first << ",";
1728            *page_stat_file << std::dec << iter.second.second << std::endl;
1729        }
1730    }
1731 }
1732
1733bool
1734ComputeUnit::isDone() const
1735{
1736    for (int i = 0; i < numSIMDs; ++i) {
1737        if (!isSimdDone(i)) {
1738            return false;
1739        }
1740    }
1741
1742    bool glbMemBusRdy = true;
1743    for (int j = 0; j < numGlbMemUnits; ++j) {
1744        glbMemBusRdy &= vrfToGlobalMemPipeBus[j].rdy();
1745    }
1746    bool locMemBusRdy = true;
1747    for (int j = 0; j < numLocMemUnits; ++j) {
1748        locMemBusRdy &= vrfToLocalMemPipeBus[j].rdy();
1749    }
1750
1751    if (!globalMemoryPipe.isGMLdRespFIFOWrRdy() ||
1752        !globalMemoryPipe.isGMStRespFIFOWrRdy() ||
1753        !globalMemoryPipe.isGMReqFIFOWrRdy() || !localMemoryPipe.isLMReqFIFOWrRdy()
1754        || !localMemoryPipe.isLMRespFIFOWrRdy() || !locMemToVrfBus.rdy() ||
1755        !glbMemToVrfBus.rdy() || !locMemBusRdy || !glbMemBusRdy) {
1756        return false;
1757    }
1758
1759    return true;
1760}
1761
1762int32_t
1763ComputeUnit::getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const
1764{
1765    return lds.getRefCounter(dispatchId, wgId);
1766}
1767
1768bool
1769ComputeUnit::isSimdDone(uint32_t simdId) const
1770{
1771    assert(simdId < numSIMDs);
1772
1773    for (int i=0; i < numGlbMemUnits; ++i) {
1774        if (!vrfToGlobalMemPipeBus[i].rdy())
1775            return false;
1776    }
1777    for (int i=0; i < numLocMemUnits; ++i) {
1778        if (!vrfToLocalMemPipeBus[i].rdy())
1779            return false;
1780    }
1781    if (!aluPipe[simdId].rdy()) {
1782        return false;
1783    }
1784
1785    for (int i_wf = 0; i_wf < shader->n_wf; ++i_wf){
1786        if (wfList[simdId][i_wf]->status != Wavefront::S_STOPPED) {
1787            return false;
1788        }
1789    }
1790
1791    return true;
1792}
1793
1794/**
1795 * send a general request to the LDS
1796 * make sure to look at the return value here as your request might be
1797 * NACK'd and returning false means that you have to have some backup plan
1798 */
1799bool
1800ComputeUnit::sendToLds(GPUDynInstPtr gpuDynInst)
1801{
1802    // this is just a request to carry the GPUDynInstPtr
1803    // back and forth
1804    Request *newRequest = new Request();
1805    newRequest->setPaddr(0x0);
1806
1807    // ReadReq is not evaluted by the LDS but the Packet ctor requires this
1808    PacketPtr newPacket = new Packet(newRequest, MemCmd::ReadReq);
1809
1810    // This is the SenderState needed upon return
1811    newPacket->senderState = new LDSPort::SenderState(gpuDynInst);
1812
1813    return ldsPort->sendTimingReq(newPacket);
1814}
1815
1816/**
1817 * get the result of packets sent to the LDS when they return
1818 */
1819bool
1820ComputeUnit::LDSPort::recvTimingResp(PacketPtr packet)
1821{
1822    const ComputeUnit::LDSPort::SenderState *senderState =
1823        dynamic_cast<ComputeUnit::LDSPort::SenderState *>(packet->senderState);
1824
1825    fatal_if(!senderState, "did not get the right sort of sender state");
1826
1827    GPUDynInstPtr gpuDynInst = senderState->getMemInst();
1828
1829    delete packet->senderState;
1830    delete packet->req;
1831    delete packet;
1832
1833    computeUnit->localMemoryPipe.getLMRespFIFO().push(gpuDynInst);
1834    return true;
1835}
1836
1837/**
1838 * attempt to send this packet, either the port is already stalled, the request
1839 * is nack'd and must stall or the request goes through
1840 * when a request cannot be sent, add it to the retries queue
1841 */
1842bool
1843ComputeUnit::LDSPort::sendTimingReq(PacketPtr pkt)
1844{
1845    ComputeUnit::LDSPort::SenderState *sender_state =
1846            dynamic_cast<ComputeUnit::LDSPort::SenderState*>(pkt->senderState);
1847    fatal_if(!sender_state, "packet without a valid sender state");
1848
1849    GPUDynInstPtr gpuDynInst M5_VAR_USED = sender_state->getMemInst();
1850
1851    if (isStalled()) {
1852        fatal_if(retries.empty(), "must have retries waiting to be stalled");
1853
1854        retries.push(pkt);
1855
1856        DPRINTF(GPUPort, "CU%d: WF[%d][%d]: LDS send failed!\n",
1857                        computeUnit->cu_id, gpuDynInst->simdId,
1858                        gpuDynInst->wfSlotId);
1859        return false;
1860    } else if (!MasterPort::sendTimingReq(pkt)) {
1861        // need to stall the LDS port until a recvReqRetry() is received
1862        // this indicates that there is more space
1863        stallPort();
1864        retries.push(pkt);
1865
1866        DPRINTF(GPUPort, "CU%d: WF[%d][%d]: addr %#x lds req failed!\n",
1867                computeUnit->cu_id, gpuDynInst->simdId,
1868                gpuDynInst->wfSlotId, pkt->req->getPaddr());
1869        return false;
1870    } else {
1871        DPRINTF(GPUPort, "CU%d: WF[%d][%d]: addr %#x lds req sent!\n",
1872                computeUnit->cu_id, gpuDynInst->simdId,
1873                gpuDynInst->wfSlotId, pkt->req->getPaddr());
1874        return true;
1875    }
1876}
1877
1878/**
1879 * the bus is telling the port that there is now space so retrying stalled
1880 * requests should work now
1881 * this allows the port to have a request be nack'd and then have the receiver
1882 * say when there is space, rather than simply retrying the send every cycle
1883 */
1884void
1885ComputeUnit::LDSPort::recvReqRetry()
1886{
1887    auto queueSize = retries.size();
1888
1889    DPRINTF(GPUPort, "CU%d: LDSPort recvReqRetry - %d pending requests\n",
1890            computeUnit->cu_id, queueSize);
1891
1892    fatal_if(queueSize < 1,
1893             "why was there a recvReqRetry() with no pending reqs?");
1894    fatal_if(!isStalled(),
1895             "recvReqRetry() happened when the port was not stalled");
1896
1897    unstallPort();
1898
1899    while (!retries.empty()) {
1900        PacketPtr packet = retries.front();
1901
1902        DPRINTF(GPUPort, "CU%d: retrying LDS send\n", computeUnit->cu_id);
1903
1904        if (!MasterPort::sendTimingReq(packet)) {
1905            // Stall port
1906            stallPort();
1907            DPRINTF(GPUPort, ": LDS send failed again\n");
1908            break;
1909        } else {
1910            DPRINTF(GPUTLB, ": LDS send successful\n");
1911            retries.pop();
1912        }
1913    }
1914}
1915