X86GPUTLB.py revision 13892 
1# Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# For use for simulation and test purposes only
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are met:
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9# 1. Redistributions of source code must retain the above copyright notice,
10# this list of conditions and the following disclaimer.
11#
12# 2. Redistributions in binary form must reproduce the above copyright notice,
13# this list of conditions and the following disclaimer in the documentation
14# and/or other materials provided with the distribution.
15#
16# 3. Neither the name of the copyright holder nor the names of its
17# contributors may be used to endorse or promote products derived from this
18# software without specific prior written permission.
19#
20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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29# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30# POSSIBILITY OF SUCH DAMAGE.
31#
32# Authors: Lisa Hsu
33
34from m5.defines import buildEnv
35from m5.params import *
36from m5.proxy import *
37
38from m5.objects.ClockedObject import ClockedObject
39from m5.SimObject import SimObject
40
41if buildEnv['FULL_SYSTEM']:
42    class X86PagetableWalker(SimObject):
43        type = 'X86PagetableWalker'
44        cxx_class = 'X86ISA::Walker'
45        port = SlavePort("Port for the hardware table walker")
46        system = Param.System(Parent.any, "system object")
47
48class X86GPUTLB(ClockedObject):
49    type = 'X86GPUTLB'
50    cxx_class = 'X86ISA::GpuTLB'
51    cxx_header = 'gpu-compute/gpu_tlb.hh'
52    size = Param.Int(64, "TLB size (number of entries)")
53    assoc = Param.Int(64, "TLB associativity")
54
55    if buildEnv['FULL_SYSTEM']:
56        walker = Param.X86PagetableWalker(X86PagetableWalker(),
57                                          "page table walker")
58
59    hitLatency = Param.Int(2, "Latency of a TLB hit")
60    missLatency1 = Param.Int(5, "Latency #1 of a TLB miss")
61    missLatency2 = Param.Int(100, "Latency #2 of a TLB miss")
62    maxOutstandingReqs = Param.Int(64, "# of maximum outstanding requests")
63    slave = VectorSlavePort("Port on side closer to CPU/CU")
64    master = VectorMasterPort("Port on side closer to memory")
65    allocationPolicy = Param.Bool(True, "Allocate on an access")
66    accessDistance = Param.Bool(False, "print accessDistance stats")
67
68class TLBCoalescer(ClockedObject):
69    type = 'TLBCoalescer'
70    cxx_class = 'TLBCoalescer'
71    cxx_header = 'gpu-compute/tlb_coalescer.hh'
72    probesPerCycle = Param.Int(2, "Number of TLB probes per cycle")
73    coalescingWindow = Param.Int(1, "Permit coalescing across that many ticks")
74    slave = VectorSlavePort("Port on side closer to CPU/CU")
75    master = VectorMasterPort("Port on side closer to memory")
76    disableCoalescing = Param.Bool(False,"Dispable Coalescing")
77