X86GPUTLB.py revision 12697:cd71b966be1e 
1# Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# For use for simulation and test purposes only
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10# this list of conditions and the following disclaimer.
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12# 2. Redistributions in binary form must reproduce the above copyright notice,
13# this list of conditions and the following disclaimer in the documentation
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20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31#
32# Authors: Lisa Hsu
33
34from m5.defines import buildEnv
35from m5.params import *
36from m5.proxy import *
37
38from m5.objects.MemObject import MemObject
39
40if buildEnv['FULL_SYSTEM']:
41    class X86PagetableWalker(MemObject):
42        type = 'X86PagetableWalker'
43        cxx_class = 'X86ISA::Walker'
44        port = SlavePort("Port for the hardware table walker")
45        system = Param.System(Parent.any, "system object")
46
47class X86GPUTLB(MemObject):
48    type = 'X86GPUTLB'
49    cxx_class = 'X86ISA::GpuTLB'
50    cxx_header = 'gpu-compute/gpu_tlb.hh'
51    size = Param.Int(64, "TLB size (number of entries)")
52    assoc = Param.Int(64, "TLB associativity")
53
54    if buildEnv['FULL_SYSTEM']:
55        walker = Param.X86PagetableWalker(X86PagetableWalker(),
56                                          "page table walker")
57
58    hitLatency = Param.Int(2, "Latency of a TLB hit")
59    missLatency1 = Param.Int(5, "Latency #1 of a TLB miss")
60    missLatency2 = Param.Int(100, "Latency #2 of a TLB miss")
61    maxOutstandingReqs = Param.Int(64, "# of maximum outstanding requests")
62    slave = VectorSlavePort("Port on side closer to CPU/CU")
63    master = VectorMasterPort("Port on side closer to memory")
64    allocationPolicy = Param.Bool(True, "Allocate on an access")
65    accessDistance = Param.Bool(False, "print accessDistance stats")
66
67class TLBCoalescer(MemObject):
68    type = 'TLBCoalescer'
69    cxx_class = 'TLBCoalescer'
70    cxx_header = 'gpu-compute/tlb_coalescer.hh'
71    probesPerCycle = Param.Int(2, "Number of TLB probes per cycle")
72    coalescingWindow = Param.Int(1, "Permit coalescing across that many ticks")
73    slave = VectorSlavePort("Port on side closer to CPU/CU")
74    master = VectorMasterPort("Port on side closer to memory")
75    disableCoalescing = Param.Bool(False,"Dispable Coalescing")
76