GPU.py revision 13665
111308Santhony.gutierrez@amd.com#
211308Santhony.gutierrez@amd.com#  Copyright (c) 2015 Advanced Micro Devices, Inc.
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411308Santhony.gutierrez@amd.com#
511308Santhony.gutierrez@amd.com#  For use for simulation and test purposes only
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911308Santhony.gutierrez@amd.com#
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3211308Santhony.gutierrez@amd.com#
3311308Santhony.gutierrez@amd.com#  Author: Steve Reinhardt
3411308Santhony.gutierrez@amd.com#
3511308Santhony.gutierrez@amd.com
3611308Santhony.gutierrez@amd.comfrom m5.defines import buildEnv
3711308Santhony.gutierrez@amd.comfrom m5.params import *
3811308Santhony.gutierrez@amd.comfrom m5.proxy import *
3911308Santhony.gutierrez@amd.comfrom m5.SimObject import SimObject
4013665Sandreas.sandberg@arm.com
4113665Sandreas.sandberg@arm.comfrom m5.objects.ClockedObject import ClockedObject
4213665Sandreas.sandberg@arm.comfrom m5.objects.Device import DmaDevice
4313665Sandreas.sandberg@arm.comfrom m5.objects.MemObject import MemObject
4413665Sandreas.sandberg@arm.comfrom m5.objects.Process import EmulatedDriver
4513665Sandreas.sandberg@arm.comfrom m5.objects.Bridge import Bridge
4613665Sandreas.sandberg@arm.comfrom m5.objects.LdsState import LdsState
4711308Santhony.gutierrez@amd.com
4811308Santhony.gutierrez@amd.comclass PrefetchType(Enum): vals = [
4911308Santhony.gutierrez@amd.com    'PF_CU',
5011308Santhony.gutierrez@amd.com    'PF_PHASE',
5111308Santhony.gutierrez@amd.com    'PF_WF',
5211308Santhony.gutierrez@amd.com    'PF_STRIDE',
5311308Santhony.gutierrez@amd.com    'PF_END',
5411308Santhony.gutierrez@amd.com    ]
5511308Santhony.gutierrez@amd.com
5611308Santhony.gutierrez@amd.comclass VectorRegisterFile(SimObject):
5711308Santhony.gutierrez@amd.com    type = 'VectorRegisterFile'
5811308Santhony.gutierrez@amd.com    cxx_class = 'VectorRegisterFile'
5911308Santhony.gutierrez@amd.com    cxx_header = 'gpu-compute/vector_register_file.hh'
6011308Santhony.gutierrez@amd.com
6111308Santhony.gutierrez@amd.com    simd_id = Param.Int(0, 'SIMD ID associated with this VRF')
6211308Santhony.gutierrez@amd.com    num_regs_per_simd = Param.Int(2048, 'number of vector registers per SIMD')
6311534Sjohn.kalamatianos@amd.com    wfSize = Param.Int(64, 'Wavefront size (in work items)')
6411308Santhony.gutierrez@amd.com    min_alloc = Param.Int(4, 'min number of VGPRs allocated per WF')
6511308Santhony.gutierrez@amd.com
6611308Santhony.gutierrez@amd.comclass Wavefront(SimObject):
6711308Santhony.gutierrez@amd.com    type = 'Wavefront'
6811308Santhony.gutierrez@amd.com    cxx_class = 'Wavefront'
6911308Santhony.gutierrez@amd.com    cxx_header = 'gpu-compute/wavefront.hh'
7011308Santhony.gutierrez@amd.com
7111308Santhony.gutierrez@amd.com    simdId = Param.Int('SIMD id (0-ComputeUnit.num_SIMDs)')
7211308Santhony.gutierrez@amd.com    wf_slot_id = Param.Int('wavefront id (0-ComputeUnit.max_wfs)')
7311534Sjohn.kalamatianos@amd.com    wfSize = Param.Int(64, 'Wavefront size (in work items)')
7411308Santhony.gutierrez@amd.com
7511308Santhony.gutierrez@amd.comclass ComputeUnit(MemObject):
7611308Santhony.gutierrez@amd.com    type = 'ComputeUnit'
7711308Santhony.gutierrez@amd.com    cxx_class = 'ComputeUnit'
7811308Santhony.gutierrez@amd.com    cxx_header = 'gpu-compute/compute_unit.hh'
7911308Santhony.gutierrez@amd.com
8011308Santhony.gutierrez@amd.com    wavefronts = VectorParam.Wavefront('Number of wavefronts')
8111308Santhony.gutierrez@amd.com    wfSize = Param.Int(64, 'Wavefront size (in work items)')
8211308Santhony.gutierrez@amd.com    num_SIMDs = Param.Int(4, 'number of SIMD units per CU')
8311308Santhony.gutierrez@amd.com
8411308Santhony.gutierrez@amd.com    spbypass_pipe_length = Param.Int(4, 'vector ALU Single Precision bypass '\
8511308Santhony.gutierrez@amd.com                                        'latency')
8611308Santhony.gutierrez@amd.com
8711308Santhony.gutierrez@amd.com    dpbypass_pipe_length = Param.Int(8, 'vector ALU Double Precision bypass '\
8811308Santhony.gutierrez@amd.com                                        'latency')
8911308Santhony.gutierrez@amd.com
9011308Santhony.gutierrez@amd.com    issue_period = Param.Int(4, 'number of cycles per issue period')
9111308Santhony.gutierrez@amd.com    num_global_mem_pipes = Param.Int(1,'number of global memory pipes per CU')
9211308Santhony.gutierrez@amd.com    num_shared_mem_pipes = Param.Int(1,'number of shared memory pipes per CU')
9311308Santhony.gutierrez@amd.com    n_wf = Param.Int(1, 'Number of wavefront slots per SIMD')
9411308Santhony.gutierrez@amd.com    mem_req_latency = Param.Int(9, "Latency for request from the cu to ruby. "\
9511308Santhony.gutierrez@amd.com                                "Represents the pipeline to reach the TCP and "\
9611308Santhony.gutierrez@amd.com                                "specified in GPU clock cycles")
9711308Santhony.gutierrez@amd.com    mem_resp_latency = Param.Int(9, "Latency for responses from ruby to the "\
9811308Santhony.gutierrez@amd.com                                 "cu. Represents the pipeline between the TCP "\
9911308Santhony.gutierrez@amd.com                                 "and cu as well as TCP data array access. "\
10011308Santhony.gutierrez@amd.com                                 "Specified in GPU clock cycles")
10111308Santhony.gutierrez@amd.com    system = Param.System(Parent.any, "system object")
10211308Santhony.gutierrez@amd.com    cu_id = Param.Int('CU id')
10311308Santhony.gutierrez@amd.com    vrf_to_coalescer_bus_width = Param.Int(32, "VRF->Coalescer data bus width "\
10411308Santhony.gutierrez@amd.com                                           "in bytes")
10511308Santhony.gutierrez@amd.com    coalescer_to_vrf_bus_width = Param.Int(32, "Coalescer->VRF data bus width "\
10611308Santhony.gutierrez@amd.com                                           "in bytes")
10711308Santhony.gutierrez@amd.com
10811308Santhony.gutierrez@amd.com    memory_port = VectorMasterPort("Port to the memory system")
10911308Santhony.gutierrez@amd.com    translation_port = VectorMasterPort('Port to the TLB hierarchy')
11011308Santhony.gutierrez@amd.com    sqc_port = MasterPort("Port to the SQC (I-cache")
11111308Santhony.gutierrez@amd.com    sqc_tlb_port = MasterPort("Port to the TLB for the SQC (I-cache)")
11211308Santhony.gutierrez@amd.com    perLaneTLB = Param.Bool(False, "enable per-lane TLB")
11311308Santhony.gutierrez@amd.com    prefetch_depth = Param.Int(0, "Number of prefetches triggered at a time"\
11411308Santhony.gutierrez@amd.com                               "(0 turns off prefetching)")
11511308Santhony.gutierrez@amd.com    prefetch_stride = Param.Int(1, "Fixed Prefetch Stride (1 means next-page)")
11611308Santhony.gutierrez@amd.com    prefetch_prev_type = Param.PrefetchType('PF_PHASE', "Prefetch the stride "\
11711308Santhony.gutierrez@amd.com                                            "from last mem req in lane of "\
11811308Santhony.gutierrez@amd.com                                            "CU|Phase|Wavefront")
11911308Santhony.gutierrez@amd.com    execPolicy = Param.String("OLDEST-FIRST", "WF execution selection policy");
12011308Santhony.gutierrez@amd.com    xactCasMode = Param.Bool(False, "Behavior of xact_cas_load magic instr.");
12111308Santhony.gutierrez@amd.com    debugSegFault = Param.Bool(False, "enable debugging GPU seg faults")
12211308Santhony.gutierrez@amd.com    functionalTLB = Param.Bool(False, "Assume TLB causes no delay")
12311308Santhony.gutierrez@amd.com
12411308Santhony.gutierrez@amd.com    localMemBarrier = Param.Bool(False, "Assume Barriers do not wait on "\
12511308Santhony.gutierrez@amd.com                                        "kernel end")
12611308Santhony.gutierrez@amd.com
12711308Santhony.gutierrez@amd.com    countPages = Param.Bool(False, "Generate per-CU file of all pages touched "\
12811308Santhony.gutierrez@amd.com                                   "and how many times")
12911308Santhony.gutierrez@amd.com    global_mem_queue_size = Param.Int(256, "Number of entries in the global "
13011308Santhony.gutierrez@amd.com                                      "memory pipeline's queues")
13111308Santhony.gutierrez@amd.com    local_mem_queue_size = Param.Int(256, "Number of entries in the local "
13211308Santhony.gutierrez@amd.com                                      "memory pipeline's queues")
13311308Santhony.gutierrez@amd.com    ldsBus = Bridge() # the bridge between the CU and its LDS
13411308Santhony.gutierrez@amd.com    ldsPort = MasterPort("The port that goes to the LDS")
13511308Santhony.gutierrez@amd.com    localDataStore = Param.LdsState("the LDS for this CU")
13611308Santhony.gutierrez@amd.com
13711308Santhony.gutierrez@amd.com    vector_register_file = VectorParam.VectorRegisterFile("Vector register "\
13811308Santhony.gutierrez@amd.com                                                          "file")
13911700Santhony.gutierrez@amd.com    out_of_order_data_delivery = Param.Bool(False, "enable OoO data delivery"
14011700Santhony.gutierrez@amd.com                                            " in the GM pipeline")
14111308Santhony.gutierrez@amd.com
14211308Santhony.gutierrez@amd.comclass Shader(ClockedObject):
14311308Santhony.gutierrez@amd.com    type = 'Shader'
14411308Santhony.gutierrez@amd.com    cxx_class = 'Shader'
14511308Santhony.gutierrez@amd.com    cxx_header = 'gpu-compute/shader.hh'
14611308Santhony.gutierrez@amd.com
14711308Santhony.gutierrez@amd.com    CUs = VectorParam.ComputeUnit('Number of compute units')
14811308Santhony.gutierrez@amd.com    n_wf = Param.Int(1, 'Number of wavefront slots per SIMD')
14911308Santhony.gutierrez@amd.com    impl_kern_boundary_sync = Param.Bool(True, """Insert acq/rel packets into
15011308Santhony.gutierrez@amd.com                                                  ruby at kernel boundaries""")
15111308Santhony.gutierrez@amd.com    separate_acquire_release = Param.Bool(False,
15211308Santhony.gutierrez@amd.com        """Do ld_acquire/st_release generate separate requests for the
15311308Santhony.gutierrez@amd.com        acquire and release?""")
15411308Santhony.gutierrez@amd.com    globalmem = Param.MemorySize('64kB', 'Memory size')
15511308Santhony.gutierrez@amd.com    timing = Param.Bool(False, 'timing memory accesses')
15611308Santhony.gutierrez@amd.com
15711308Santhony.gutierrez@amd.com    cpu_pointer = Param.BaseCPU(NULL, "pointer to base CPU")
15811308Santhony.gutierrez@amd.com    translation = Param.Bool(False, "address translation");
15911308Santhony.gutierrez@amd.com
16011308Santhony.gutierrez@amd.comclass ClDriver(EmulatedDriver):
16111308Santhony.gutierrez@amd.com    type = 'ClDriver'
16211308Santhony.gutierrez@amd.com    cxx_header = 'gpu-compute/cl_driver.hh'
16311308Santhony.gutierrez@amd.com    codefile = VectorParam.String('code file name(s)')
16411308Santhony.gutierrez@amd.com
16511308Santhony.gutierrez@amd.comclass GpuDispatcher(DmaDevice):
16611308Santhony.gutierrez@amd.com    type = 'GpuDispatcher'
16711308Santhony.gutierrez@amd.com    cxx_header = 'gpu-compute/dispatcher.hh'
16811308Santhony.gutierrez@amd.com    # put at 8GB line for now
16911308Santhony.gutierrez@amd.com    pio_addr = Param.Addr(0x200000000, "Device Address")
17011308Santhony.gutierrez@amd.com    pio_latency = Param.Latency('1ns', "Programmed IO latency")
17111308Santhony.gutierrez@amd.com    shader_pointer = Param.Shader('pointer to shader')
17211308Santhony.gutierrez@amd.com    translation_port = MasterPort('Port to the dispatcher TLB')
17311308Santhony.gutierrez@amd.com    cpu = Param.BaseCPU("CPU to wake up on kernel completion")
17411308Santhony.gutierrez@amd.com
17511308Santhony.gutierrez@amd.com    cl_driver = Param.ClDriver('pointer to driver')
17611308Santhony.gutierrez@amd.com
17711308Santhony.gutierrez@amd.comclass MemType(Enum): vals = [
17811308Santhony.gutierrez@amd.com    'M_U8',
17911308Santhony.gutierrez@amd.com    'M_U16',
18011308Santhony.gutierrez@amd.com    'M_U32',
18111308Santhony.gutierrez@amd.com    'M_U64',
18211308Santhony.gutierrez@amd.com    'M_S8',
18311308Santhony.gutierrez@amd.com    'M_S16',
18411308Santhony.gutierrez@amd.com    'M_S32',
18511308Santhony.gutierrez@amd.com    'M_S64',
18611308Santhony.gutierrez@amd.com    'M_F16',
18711308Santhony.gutierrez@amd.com    'M_F32',
18811308Santhony.gutierrez@amd.com    'M_F64',
18911308Santhony.gutierrez@amd.com    ]
19011308Santhony.gutierrez@amd.com
19111308Santhony.gutierrez@amd.comclass StorageClassType(Enum): vals = [
19211308Santhony.gutierrez@amd.com    'SC_SPILL',
19311308Santhony.gutierrez@amd.com    'SC_GLOBAL',
19411308Santhony.gutierrez@amd.com    'SC_SHARED',
19511308Santhony.gutierrez@amd.com    'SC_PRIVATE',
19611308Santhony.gutierrez@amd.com    'SC_READONLY',
19711308Santhony.gutierrez@amd.com    'SC_KERNARG',
19811308Santhony.gutierrez@amd.com    'SC_NONE',
19911308Santhony.gutierrez@amd.com    ]
20011308Santhony.gutierrez@amd.com
20111308Santhony.gutierrez@amd.comclass RegisterType(Enum): vals = [
20211308Santhony.gutierrez@amd.com    'RT_VECTOR',
20311308Santhony.gutierrez@amd.com    'RT_SCALAR',
20411308Santhony.gutierrez@amd.com    'RT_CONDITION',
20511308Santhony.gutierrez@amd.com    'RT_HARDWARE',
20611308Santhony.gutierrez@amd.com    'RT_NONE',
20711308Santhony.gutierrez@amd.com    ]
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