GPU.py revision 11308
111308Santhony.gutierrez@amd.com#
211308Santhony.gutierrez@amd.com#  Copyright (c) 2015 Advanced Micro Devices, Inc.
311308Santhony.gutierrez@amd.com#  All rights reserved.
411308Santhony.gutierrez@amd.com#
511308Santhony.gutierrez@amd.com#  For use for simulation and test purposes only
611308Santhony.gutierrez@amd.com#
711308Santhony.gutierrez@amd.com#  Redistribution and use in source and binary forms, with or without
811308Santhony.gutierrez@amd.com#  modification, are permitted provided that the following conditions are met:
911308Santhony.gutierrez@amd.com#
1011308Santhony.gutierrez@amd.com#  1. Redistributions of source code must retain the above copyright notice,
1111308Santhony.gutierrez@amd.com#  this list of conditions and the following disclaimer.
1211308Santhony.gutierrez@amd.com#
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1411308Santhony.gutierrez@amd.com#  this list of conditions and the following disclaimer in the documentation
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1611308Santhony.gutierrez@amd.com#
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1811308Santhony.gutierrez@amd.com#  may be used to endorse or promote products derived from this software
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3211308Santhony.gutierrez@amd.com#
3311308Santhony.gutierrez@amd.com#  Author: Steve Reinhardt
3411308Santhony.gutierrez@amd.com#
3511308Santhony.gutierrez@amd.com
3611308Santhony.gutierrez@amd.comfrom ClockedObject import ClockedObject
3711308Santhony.gutierrez@amd.comfrom Device import DmaDevice
3811308Santhony.gutierrez@amd.comfrom m5.defines import buildEnv
3911308Santhony.gutierrez@amd.comfrom m5.params import *
4011308Santhony.gutierrez@amd.comfrom m5.proxy import *
4111308Santhony.gutierrez@amd.comfrom m5.SimObject import SimObject
4211308Santhony.gutierrez@amd.comfrom MemObject import MemObject
4311308Santhony.gutierrez@amd.comfrom Process import EmulatedDriver
4411308Santhony.gutierrez@amd.comfrom Bridge import Bridge
4511308Santhony.gutierrez@amd.comfrom LdsState import LdsState
4611308Santhony.gutierrez@amd.com
4711308Santhony.gutierrez@amd.comclass PrefetchType(Enum): vals = [
4811308Santhony.gutierrez@amd.com    'PF_CU',
4911308Santhony.gutierrez@amd.com    'PF_PHASE',
5011308Santhony.gutierrez@amd.com    'PF_WF',
5111308Santhony.gutierrez@amd.com    'PF_STRIDE',
5211308Santhony.gutierrez@amd.com    'PF_END',
5311308Santhony.gutierrez@amd.com    ]
5411308Santhony.gutierrez@amd.com
5511308Santhony.gutierrez@amd.comclass VectorRegisterFile(SimObject):
5611308Santhony.gutierrez@amd.com    type = 'VectorRegisterFile'
5711308Santhony.gutierrez@amd.com    cxx_class = 'VectorRegisterFile'
5811308Santhony.gutierrez@amd.com    cxx_header = 'gpu-compute/vector_register_file.hh'
5911308Santhony.gutierrez@amd.com
6011308Santhony.gutierrez@amd.com    simd_id = Param.Int(0, 'SIMD ID associated with this VRF')
6111308Santhony.gutierrez@amd.com    num_regs_per_simd = Param.Int(2048, 'number of vector registers per SIMD')
6211308Santhony.gutierrez@amd.com    min_alloc = Param.Int(4, 'min number of VGPRs allocated per WF')
6311308Santhony.gutierrez@amd.com
6411308Santhony.gutierrez@amd.comclass Wavefront(SimObject):
6511308Santhony.gutierrez@amd.com    type = 'Wavefront'
6611308Santhony.gutierrez@amd.com    cxx_class = 'Wavefront'
6711308Santhony.gutierrez@amd.com    cxx_header = 'gpu-compute/wavefront.hh'
6811308Santhony.gutierrez@amd.com
6911308Santhony.gutierrez@amd.com    simdId = Param.Int('SIMD id (0-ComputeUnit.num_SIMDs)')
7011308Santhony.gutierrez@amd.com    wf_slot_id = Param.Int('wavefront id (0-ComputeUnit.max_wfs)')
7111308Santhony.gutierrez@amd.com
7211308Santhony.gutierrez@amd.comclass ComputeUnit(MemObject):
7311308Santhony.gutierrez@amd.com    type = 'ComputeUnit'
7411308Santhony.gutierrez@amd.com    cxx_class = 'ComputeUnit'
7511308Santhony.gutierrez@amd.com    cxx_header = 'gpu-compute/compute_unit.hh'
7611308Santhony.gutierrez@amd.com
7711308Santhony.gutierrez@amd.com    wavefronts = VectorParam.Wavefront('Number of wavefronts')
7811308Santhony.gutierrez@amd.com    wfSize = Param.Int(64, 'Wavefront size (in work items)')
7911308Santhony.gutierrez@amd.com    num_SIMDs = Param.Int(4, 'number of SIMD units per CU')
8011308Santhony.gutierrez@amd.com
8111308Santhony.gutierrez@amd.com    spbypass_pipe_length = Param.Int(4, 'vector ALU Single Precision bypass '\
8211308Santhony.gutierrez@amd.com                                        'latency')
8311308Santhony.gutierrez@amd.com
8411308Santhony.gutierrez@amd.com    dpbypass_pipe_length = Param.Int(8, 'vector ALU Double Precision bypass '\
8511308Santhony.gutierrez@amd.com                                        'latency')
8611308Santhony.gutierrez@amd.com
8711308Santhony.gutierrez@amd.com    issue_period = Param.Int(4, 'number of cycles per issue period')
8811308Santhony.gutierrez@amd.com    num_global_mem_pipes = Param.Int(1,'number of global memory pipes per CU')
8911308Santhony.gutierrez@amd.com    num_shared_mem_pipes = Param.Int(1,'number of shared memory pipes per CU')
9011308Santhony.gutierrez@amd.com    n_wf = Param.Int(1, 'Number of wavefront slots per SIMD')
9111308Santhony.gutierrez@amd.com    mem_req_latency = Param.Int(9, "Latency for request from the cu to ruby. "\
9211308Santhony.gutierrez@amd.com                                "Represents the pipeline to reach the TCP and "\
9311308Santhony.gutierrez@amd.com                                "specified in GPU clock cycles")
9411308Santhony.gutierrez@amd.com    mem_resp_latency = Param.Int(9, "Latency for responses from ruby to the "\
9511308Santhony.gutierrez@amd.com                                 "cu. Represents the pipeline between the TCP "\
9611308Santhony.gutierrez@amd.com                                 "and cu as well as TCP data array access. "\
9711308Santhony.gutierrez@amd.com                                 "Specified in GPU clock cycles")
9811308Santhony.gutierrez@amd.com    system = Param.System(Parent.any, "system object")
9911308Santhony.gutierrez@amd.com    cu_id = Param.Int('CU id')
10011308Santhony.gutierrez@amd.com    vrf_to_coalescer_bus_width = Param.Int(32, "VRF->Coalescer data bus width "\
10111308Santhony.gutierrez@amd.com                                           "in bytes")
10211308Santhony.gutierrez@amd.com    coalescer_to_vrf_bus_width = Param.Int(32, "Coalescer->VRF data bus width "\
10311308Santhony.gutierrez@amd.com                                           "in bytes")
10411308Santhony.gutierrez@amd.com
10511308Santhony.gutierrez@amd.com    memory_port = VectorMasterPort("Port to the memory system")
10611308Santhony.gutierrez@amd.com    translation_port = VectorMasterPort('Port to the TLB hierarchy')
10711308Santhony.gutierrez@amd.com    sqc_port = MasterPort("Port to the SQC (I-cache")
10811308Santhony.gutierrez@amd.com    sqc_tlb_port = MasterPort("Port to the TLB for the SQC (I-cache)")
10911308Santhony.gutierrez@amd.com    perLaneTLB = Param.Bool(False, "enable per-lane TLB")
11011308Santhony.gutierrez@amd.com    prefetch_depth = Param.Int(0, "Number of prefetches triggered at a time"\
11111308Santhony.gutierrez@amd.com                               "(0 turns off prefetching)")
11211308Santhony.gutierrez@amd.com    prefetch_stride = Param.Int(1, "Fixed Prefetch Stride (1 means next-page)")
11311308Santhony.gutierrez@amd.com    prefetch_prev_type = Param.PrefetchType('PF_PHASE', "Prefetch the stride "\
11411308Santhony.gutierrez@amd.com                                            "from last mem req in lane of "\
11511308Santhony.gutierrez@amd.com                                            "CU|Phase|Wavefront")
11611308Santhony.gutierrez@amd.com    execPolicy = Param.String("OLDEST-FIRST", "WF execution selection policy");
11711308Santhony.gutierrez@amd.com    xactCasMode = Param.Bool(False, "Behavior of xact_cas_load magic instr.");
11811308Santhony.gutierrez@amd.com    debugSegFault = Param.Bool(False, "enable debugging GPU seg faults")
11911308Santhony.gutierrez@amd.com    functionalTLB = Param.Bool(False, "Assume TLB causes no delay")
12011308Santhony.gutierrez@amd.com
12111308Santhony.gutierrez@amd.com    localMemBarrier = Param.Bool(False, "Assume Barriers do not wait on "\
12211308Santhony.gutierrez@amd.com                                        "kernel end")
12311308Santhony.gutierrez@amd.com
12411308Santhony.gutierrez@amd.com    countPages = Param.Bool(False, "Generate per-CU file of all pages touched "\
12511308Santhony.gutierrez@amd.com                                   "and how many times")
12611308Santhony.gutierrez@amd.com    global_mem_queue_size = Param.Int(256, "Number of entries in the global "
12711308Santhony.gutierrez@amd.com                                      "memory pipeline's queues")
12811308Santhony.gutierrez@amd.com    local_mem_queue_size = Param.Int(256, "Number of entries in the local "
12911308Santhony.gutierrez@amd.com                                      "memory pipeline's queues")
13011308Santhony.gutierrez@amd.com    ldsBus = Bridge() # the bridge between the CU and its LDS
13111308Santhony.gutierrez@amd.com    ldsPort = MasterPort("The port that goes to the LDS")
13211308Santhony.gutierrez@amd.com    localDataStore = Param.LdsState("the LDS for this CU")
13311308Santhony.gutierrez@amd.com
13411308Santhony.gutierrez@amd.com    vector_register_file = VectorParam.VectorRegisterFile("Vector register "\
13511308Santhony.gutierrez@amd.com                                                          "file")
13611308Santhony.gutierrez@amd.com
13711308Santhony.gutierrez@amd.comclass Shader(ClockedObject):
13811308Santhony.gutierrez@amd.com    type = 'Shader'
13911308Santhony.gutierrez@amd.com    cxx_class = 'Shader'
14011308Santhony.gutierrez@amd.com    cxx_header = 'gpu-compute/shader.hh'
14111308Santhony.gutierrez@amd.com
14211308Santhony.gutierrez@amd.com    CUs = VectorParam.ComputeUnit('Number of compute units')
14311308Santhony.gutierrez@amd.com    n_wf = Param.Int(1, 'Number of wavefront slots per SIMD')
14411308Santhony.gutierrez@amd.com    impl_kern_boundary_sync = Param.Bool(True, """Insert acq/rel packets into
14511308Santhony.gutierrez@amd.com                                                  ruby at kernel boundaries""")
14611308Santhony.gutierrez@amd.com    separate_acquire_release = Param.Bool(False,
14711308Santhony.gutierrez@amd.com        """Do ld_acquire/st_release generate separate requests for the
14811308Santhony.gutierrez@amd.com        acquire and release?""")
14911308Santhony.gutierrez@amd.com    globalmem = Param.MemorySize('64kB', 'Memory size')
15011308Santhony.gutierrez@amd.com    timing = Param.Bool(False, 'timing memory accesses')
15111308Santhony.gutierrez@amd.com
15211308Santhony.gutierrez@amd.com    cpu_pointer = Param.BaseCPU(NULL, "pointer to base CPU")
15311308Santhony.gutierrez@amd.com    translation = Param.Bool(False, "address translation");
15411308Santhony.gutierrez@amd.com
15511308Santhony.gutierrez@amd.comclass ClDriver(EmulatedDriver):
15611308Santhony.gutierrez@amd.com    type = 'ClDriver'
15711308Santhony.gutierrez@amd.com    cxx_header = 'gpu-compute/cl_driver.hh'
15811308Santhony.gutierrez@amd.com    codefile = VectorParam.String('code file name(s)')
15911308Santhony.gutierrez@amd.com
16011308Santhony.gutierrez@amd.comclass GpuDispatcher(DmaDevice):
16111308Santhony.gutierrez@amd.com    type = 'GpuDispatcher'
16211308Santhony.gutierrez@amd.com    cxx_header = 'gpu-compute/dispatcher.hh'
16311308Santhony.gutierrez@amd.com    # put at 8GB line for now
16411308Santhony.gutierrez@amd.com    pio_addr = Param.Addr(0x200000000, "Device Address")
16511308Santhony.gutierrez@amd.com    pio_latency = Param.Latency('1ns', "Programmed IO latency")
16611308Santhony.gutierrez@amd.com    shader_pointer = Param.Shader('pointer to shader')
16711308Santhony.gutierrez@amd.com    translation_port = MasterPort('Port to the dispatcher TLB')
16811308Santhony.gutierrez@amd.com    cpu = Param.BaseCPU("CPU to wake up on kernel completion")
16911308Santhony.gutierrez@amd.com
17011308Santhony.gutierrez@amd.com    cl_driver = Param.ClDriver('pointer to driver')
17111308Santhony.gutierrez@amd.com
17211308Santhony.gutierrez@amd.comclass OpType(Enum): vals = [
17311308Santhony.gutierrez@amd.com    'OT_NULL',
17411308Santhony.gutierrez@amd.com    'OT_ALU',
17511308Santhony.gutierrez@amd.com    'OT_SPECIAL',
17611308Santhony.gutierrez@amd.com    'OT_GLOBAL_READ',
17711308Santhony.gutierrez@amd.com    'OT_GLOBAL_WRITE',
17811308Santhony.gutierrez@amd.com    'OT_GLOBAL_ATOMIC',
17911308Santhony.gutierrez@amd.com    'OT_GLOBAL_HIST',
18011308Santhony.gutierrez@amd.com    'OT_GLOBAL_LDAS',
18111308Santhony.gutierrez@amd.com    'OT_SHARED_READ',
18211308Santhony.gutierrez@amd.com    'OT_SHARED_WRITE',
18311308Santhony.gutierrez@amd.com    'OT_SHARED_ATOMIC',
18411308Santhony.gutierrez@amd.com    'OT_SHARED_HIST',
18511308Santhony.gutierrez@amd.com    'OT_SHARED_LDAS',
18611308Santhony.gutierrez@amd.com    'OT_PRIVATE_READ',
18711308Santhony.gutierrez@amd.com    'OT_PRIVATE_WRITE',
18811308Santhony.gutierrez@amd.com    'OT_PRIVATE_ATOMIC',
18911308Santhony.gutierrez@amd.com    'OT_PRIVATE_HIST',
19011308Santhony.gutierrez@amd.com    'OT_PRIVATE_LDAS',
19111308Santhony.gutierrez@amd.com    'OT_SPILL_READ',
19211308Santhony.gutierrez@amd.com    'OT_SPILL_WRITE',
19311308Santhony.gutierrez@amd.com    'OT_SPILL_ATOMIC',
19411308Santhony.gutierrez@amd.com    'OT_SPILL_HIST',
19511308Santhony.gutierrez@amd.com    'OT_SPILL_LDAS',
19611308Santhony.gutierrez@amd.com    'OT_READONLY_READ',
19711308Santhony.gutierrez@amd.com    'OT_READONLY_WRITE',
19811308Santhony.gutierrez@amd.com    'OT_READONLY_ATOMIC',
19911308Santhony.gutierrez@amd.com    'OT_READONLY_HIST',
20011308Santhony.gutierrez@amd.com    'OT_READONLY_LDAS',
20111308Santhony.gutierrez@amd.com    'OT_FLAT_READ',
20211308Santhony.gutierrez@amd.com    'OT_FLAT_WRITE',
20311308Santhony.gutierrez@amd.com    'OT_FLAT_ATOMIC',
20411308Santhony.gutierrez@amd.com    'OT_FLAT_HIST',
20511308Santhony.gutierrez@amd.com    'OT_FLAT_LDAS',
20611308Santhony.gutierrez@amd.com    'OT_KERN_READ',
20711308Santhony.gutierrez@amd.com    'OT_BRANCH',
20811308Santhony.gutierrez@amd.com
20911308Santhony.gutierrez@amd.com    # note: Only the OT_BOTH_MEMFENCE seems to be supported in the 1.0F version
21011308Santhony.gutierrez@amd.com    #       of the compiler.
21111308Santhony.gutierrez@amd.com    'OT_SHARED_MEMFENCE',
21211308Santhony.gutierrez@amd.com    'OT_GLOBAL_MEMFENCE',
21311308Santhony.gutierrez@amd.com    'OT_BOTH_MEMFENCE',
21411308Santhony.gutierrez@amd.com
21511308Santhony.gutierrez@amd.com    'OT_BARRIER',
21611308Santhony.gutierrez@amd.com    'OT_PRINT',
21711308Santhony.gutierrez@amd.com    'OT_RET',
21811308Santhony.gutierrez@amd.com    'OT_NOP',
21911308Santhony.gutierrez@amd.com    'OT_ARG'
22011308Santhony.gutierrez@amd.com    ]
22111308Santhony.gutierrez@amd.com
22211308Santhony.gutierrez@amd.comclass MemType(Enum): vals = [
22311308Santhony.gutierrez@amd.com    'M_U8',
22411308Santhony.gutierrez@amd.com    'M_U16',
22511308Santhony.gutierrez@amd.com    'M_U32',
22611308Santhony.gutierrez@amd.com    'M_U64',
22711308Santhony.gutierrez@amd.com    'M_S8',
22811308Santhony.gutierrez@amd.com    'M_S16',
22911308Santhony.gutierrez@amd.com    'M_S32',
23011308Santhony.gutierrez@amd.com    'M_S64',
23111308Santhony.gutierrez@amd.com    'M_F16',
23211308Santhony.gutierrez@amd.com    'M_F32',
23311308Santhony.gutierrez@amd.com    'M_F64',
23411308Santhony.gutierrez@amd.com    ]
23511308Santhony.gutierrez@amd.com
23611308Santhony.gutierrez@amd.comclass MemOpType(Enum): vals = [
23711308Santhony.gutierrez@amd.com    'MO_LD',
23811308Santhony.gutierrez@amd.com    'MO_ST',
23911308Santhony.gutierrez@amd.com    'MO_LDAS',
24011308Santhony.gutierrez@amd.com    'MO_LDA',
24111308Santhony.gutierrez@amd.com    'MO_AAND',
24211308Santhony.gutierrez@amd.com    'MO_AOR',
24311308Santhony.gutierrez@amd.com    'MO_AXOR',
24411308Santhony.gutierrez@amd.com    'MO_ACAS',
24511308Santhony.gutierrez@amd.com    'MO_AEXCH',
24611308Santhony.gutierrez@amd.com    'MO_AADD',
24711308Santhony.gutierrez@amd.com    'MO_ASUB',
24811308Santhony.gutierrez@amd.com    'MO_AINC',
24911308Santhony.gutierrez@amd.com    'MO_ADEC',
25011308Santhony.gutierrez@amd.com    'MO_AMAX',
25111308Santhony.gutierrez@amd.com    'MO_AMIN',
25211308Santhony.gutierrez@amd.com    'MO_ANRAND',
25311308Santhony.gutierrez@amd.com    'MO_ANROR',
25411308Santhony.gutierrez@amd.com    'MO_ANRXOR',
25511308Santhony.gutierrez@amd.com    'MO_ANRCAS',
25611308Santhony.gutierrez@amd.com    'MO_ANREXCH',
25711308Santhony.gutierrez@amd.com    'MO_ANRADD',
25811308Santhony.gutierrez@amd.com    'MO_ANRSUB',
25911308Santhony.gutierrez@amd.com    'MO_ANRINC',
26011308Santhony.gutierrez@amd.com    'MO_ANRDEC',
26111308Santhony.gutierrez@amd.com    'MO_ANRMAX',
26211308Santhony.gutierrez@amd.com    'MO_ANRMIN',
26311308Santhony.gutierrez@amd.com    'MO_HAND',
26411308Santhony.gutierrez@amd.com    'MO_HOR',
26511308Santhony.gutierrez@amd.com    'MO_HXOR',
26611308Santhony.gutierrez@amd.com    'MO_HCAS',
26711308Santhony.gutierrez@amd.com    'MO_HEXCH',
26811308Santhony.gutierrez@amd.com    'MO_HADD',
26911308Santhony.gutierrez@amd.com    'MO_HSUB',
27011308Santhony.gutierrez@amd.com    'MO_HINC',
27111308Santhony.gutierrez@amd.com    'MO_HDEC',
27211308Santhony.gutierrez@amd.com    'MO_HMAX',
27311308Santhony.gutierrez@amd.com    'MO_HMIN',
27411308Santhony.gutierrez@amd.com    'MO_UNDEF'
27511308Santhony.gutierrez@amd.com    ]
27611308Santhony.gutierrez@amd.com
27711308Santhony.gutierrez@amd.comclass StorageClassType(Enum): vals = [
27811308Santhony.gutierrez@amd.com    'SC_SPILL',
27911308Santhony.gutierrez@amd.com    'SC_GLOBAL',
28011308Santhony.gutierrez@amd.com    'SC_SHARED',
28111308Santhony.gutierrez@amd.com    'SC_PRIVATE',
28211308Santhony.gutierrez@amd.com    'SC_READONLY',
28311308Santhony.gutierrez@amd.com    'SC_KERNARG',
28411308Santhony.gutierrez@amd.com    'SC_NONE',
28511308Santhony.gutierrez@amd.com    ]
28611308Santhony.gutierrez@amd.com
28711308Santhony.gutierrez@amd.comclass RegisterType(Enum): vals = [
28811308Santhony.gutierrez@amd.com    'RT_VECTOR',
28911308Santhony.gutierrez@amd.com    'RT_SCALAR',
29011308Santhony.gutierrez@amd.com    'RT_CONDITION',
29111308Santhony.gutierrez@amd.com    'RT_HARDWARE',
29211308Santhony.gutierrez@amd.com    'RT_NONE',
29311308Santhony.gutierrez@amd.com    ]
29411308Santhony.gutierrez@amd.com
29511308Santhony.gutierrez@amd.comclass GenericMemoryOrder(Enum): vals = [
29611308Santhony.gutierrez@amd.com    'MEMORY_ORDER_NONE',
29711308Santhony.gutierrez@amd.com    'MEMORY_ORDER_RELAXED',
29811308Santhony.gutierrez@amd.com    'MEMORY_ORDER_SC_ACQUIRE',
29911308Santhony.gutierrez@amd.com    'MEMORY_ORDER_SC_RELEASE',
30011308Santhony.gutierrez@amd.com    'MEMORY_ORDER_SC_ACQUIRE_RELEASE',
30111308Santhony.gutierrez@amd.com    ]
30211308Santhony.gutierrez@amd.com
30311308Santhony.gutierrez@amd.comclass GenericMemoryScope(Enum): vals = [
30411308Santhony.gutierrez@amd.com    'MEMORY_SCOPE_NONE',
30511308Santhony.gutierrez@amd.com    'MEMORY_SCOPE_WORKITEM',
30611308Santhony.gutierrez@amd.com    'MEMORY_SCOPE_WAVEFRONT',
30711308Santhony.gutierrez@amd.com    'MEMORY_SCOPE_WORKGROUP',
30811308Santhony.gutierrez@amd.com    'MEMORY_SCOPE_DEVICE',
30911308Santhony.gutierrez@amd.com    'MEMORY_SCOPE_SYSTEM',
31011308Santhony.gutierrez@amd.com    ]
311