pc.cc revision 5829:2fdbb27f8c70 
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31/** @file
32 * Implementation of PC platform.
33 */
34
35#include <deque>
36#include <string>
37#include <vector>
38
39#include "arch/x86/intmessage.hh"
40#include "arch/x86/x86_traits.hh"
41#include "cpu/intr_control.hh"
42#include "dev/terminal.hh"
43#include "dev/x86/i82094aa.hh"
44#include "dev/x86/i8254.hh"
45#include "dev/x86/pc.hh"
46#include "dev/x86/south_bridge.hh"
47#include "sim/system.hh"
48
49using namespace std;
50using namespace TheISA;
51
52Pc::Pc(const Params *p)
53    : Platform(p), system(p->system)
54{
55    southBridge = NULL;
56    // set the back pointer from the system to myself
57    system->platform = this;
58}
59
60void
61Pc::init()
62{
63    assert(southBridge);
64
65    /*
66     * Initialize the timer.
67     */
68    I8254 & timer = *southBridge->pit;
69    //Timer 0, mode 2, no bcd, 16 bit count
70    timer.writeControl(0x34);
71    //Timer 0, latch command
72    timer.writeControl(0x00);
73    //Write a 16 bit count of 0
74    timer.writeCounter(0, 0);
75    timer.writeCounter(0, 0);
76
77    /*
78     * Initialize the I/O APIC.
79     */
80    I82094AA & ioApic = *southBridge->ioApic;
81    I82094AA::RedirTableEntry entry = 0;
82    entry.deliveryMode = DeliveryMode::ExtInt;
83    entry.vector = 0x20;
84    ioApic.writeReg(0x10, entry.bottomDW);
85    ioApic.writeReg(0x11, entry.topDW);
86    entry.deliveryMode = DeliveryMode::Fixed;
87    entry.vector = 0x24;
88    ioApic.writeReg(0x18, entry.bottomDW);
89    ioApic.writeReg(0x19, entry.topDW);
90    entry.mask = 1;
91    entry.vector = 0x21;
92    ioApic.writeReg(0x12, entry.bottomDW);
93    ioApic.writeReg(0x13, entry.topDW);
94    entry.vector = 0x20;
95    ioApic.writeReg(0x14, entry.bottomDW);
96    ioApic.writeReg(0x15, entry.topDW);
97    entry.vector = 0x28;
98    ioApic.writeReg(0x20, entry.bottomDW);
99    ioApic.writeReg(0x21, entry.topDW);
100    entry.vector = 0x2C;
101    ioApic.writeReg(0x28, entry.bottomDW);
102    ioApic.writeReg(0x29, entry.topDW);
103}
104
105Tick
106Pc::intrFrequency()
107{
108    panic("Need implementation\n");
109    M5_DUMMY_RETURN
110}
111
112void
113Pc::postConsoleInt()
114{
115    warn_once("Don't know what interrupt to post for console.\n");
116    //panic("Need implementation\n");
117}
118
119void
120Pc::clearConsoleInt()
121{
122    warn_once("Don't know what interrupt to clear for console.\n");
123    //panic("Need implementation\n");
124}
125
126void
127Pc::postPciInt(int line)
128{
129    panic("Need implementation\n");
130}
131
132void
133Pc::clearPciInt(int line)
134{
135    panic("Need implementation\n");
136}
137
138Addr
139Pc::pciToDma(Addr pciAddr) const
140{
141    panic("Need implementation\n");
142    M5_DUMMY_RETURN
143}
144
145
146Addr
147Pc::calcConfigAddr(int bus, int dev, int func)
148{
149    assert(func < 8);
150    assert(dev < 32);
151    assert(bus == 0);
152    return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
153}
154
155Pc *
156PcParams::create()
157{
158    return new Pc(this);
159}
160