pc.cc revision 11793:ef606668d247
15390SN/A/* 25452SN/A * Copyright (c) 2008 The Regents of The University of Michigan 35390SN/A * All rights reserved. 45390SN/A * 55390SN/A * Redistribution and use in source and binary forms, with or without 65390SN/A * modification, are permitted provided that the following conditions are 75390SN/A * met: redistributions of source code must retain the above copyright 85390SN/A * notice, this list of conditions and the following disclaimer; 95390SN/A * redistributions in binary form must reproduce the above copyright 105390SN/A * notice, this list of conditions and the following disclaimer in the 115390SN/A * documentation and/or other materials provided with the distribution; 125390SN/A * neither the name of the copyright holders nor the names of its 135390SN/A * contributors may be used to endorse or promote products derived from 145390SN/A * this software without specific prior written permission. 155390SN/A * 165390SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175390SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185390SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195390SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205390SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215390SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225390SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235390SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245390SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255390SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265390SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275390SN/A * 285390SN/A * Authors: Gabe Black 295390SN/A */ 305390SN/A 315629Sgblack@eecs.umich.edu/** @file 325629Sgblack@eecs.umich.edu * Implementation of PC platform. 335390SN/A */ 345629Sgblack@eecs.umich.edu 355393SN/A#include "dev/x86/pc.hh" 365629Sgblack@eecs.umich.edu 375390SN/A#include <deque> 385390SN/A#include <string> 395390SN/A#include <vector> 405390SN/A 415629Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 425390SN/A#include "arch/x86/x86_traits.hh" 435390SN/A#include "config/the_isa.hh" 445629Sgblack@eecs.umich.edu#include "cpu/intr_control.hh" 455629Sgblack@eecs.umich.edu#include "dev/terminal.hh" 465390SN/A#include "dev/x86/i82094aa.hh" 475390SN/A#include "dev/x86/i8254.hh" 485390SN/A#include "dev/x86/i8259.hh" 495390SN/A#include "dev/x86/south_bridge.hh" 505390SN/A#include "sim/system.hh" 515390SN/A 525390SN/Ausing namespace std; 535390SN/Ausing namespace TheISA; 545390SN/A 555393SN/APc::Pc(const Params *p) 565393SN/A : Platform(p), system(p->system) 575393SN/A{ 585611SN/A southBridge = NULL; 595611SN/A} 605611SN/A 615393SN/Avoid 625393SN/APc::init() 635393SN/A{ 645393SN/A assert(southBridge); 655393SN/A 665393SN/A /* 675393SN/A * Initialize the timer. 685393SN/A */ 695393SN/A I8254 & timer = *southBridge->pit; 705390SN/A //Timer 0, mode 2, no bcd, 16 bit count 715629Sgblack@eecs.umich.edu timer.writeControl(0x34); 725390SN/A //Timer 0, latch command 735629Sgblack@eecs.umich.edu timer.writeControl(0x00); 745629Sgblack@eecs.umich.edu //Write a 16 bit count of 0 755390SN/A timer.writeCounter(0, 0); 765629Sgblack@eecs.umich.edu timer.writeCounter(0, 0); 775390SN/A 785390SN/A /* 795390SN/A * Initialize the I/O APIC. 805390SN/A */ 815390SN/A I82094AA & ioApic = *southBridge->ioApic; 825390SN/A I82094AA::RedirTableEntry entry = 0; 835390SN/A entry.deliveryMode = DeliveryMode::ExtInt; 845390SN/A entry.vector = 0x20; 855390SN/A ioApic.writeReg(0x10, entry.bottomDW); 865390SN/A ioApic.writeReg(0x11, entry.topDW); 875390SN/A entry.deliveryMode = DeliveryMode::Fixed; 885629Sgblack@eecs.umich.edu entry.vector = 0x24; 89 ioApic.writeReg(0x18, entry.bottomDW); 90 ioApic.writeReg(0x19, entry.topDW); 91 entry.mask = 1; 92 entry.vector = 0x21; 93 ioApic.writeReg(0x12, entry.bottomDW); 94 ioApic.writeReg(0x13, entry.topDW); 95 entry.vector = 0x20; 96 ioApic.writeReg(0x14, entry.bottomDW); 97 ioApic.writeReg(0x15, entry.topDW); 98 entry.vector = 0x28; 99 ioApic.writeReg(0x20, entry.bottomDW); 100 ioApic.writeReg(0x21, entry.topDW); 101 entry.vector = 0x2C; 102 ioApic.writeReg(0x28, entry.bottomDW); 103 ioApic.writeReg(0x29, entry.topDW); 104 entry.vector = 0x2E; 105 ioApic.writeReg(0x2C, entry.bottomDW); 106 ioApic.writeReg(0x2D, entry.topDW); 107 entry.vector = 0x30; 108 ioApic.writeReg(0x30, entry.bottomDW); 109 ioApic.writeReg(0x31, entry.topDW); 110 111 /* 112 * Mask the PICs. I'm presuming the BIOS/bootloader would have cleared 113 * these out and masked them before passing control to the OS. 114 */ 115 southBridge->pic1->maskAll(); 116 southBridge->pic2->maskAll(); 117} 118 119void 120Pc::postConsoleInt() 121{ 122 southBridge->ioApic->signalInterrupt(4); 123 southBridge->pic1->signalInterrupt(4); 124} 125 126void 127Pc::clearConsoleInt() 128{ 129 warn_once("Don't know what interrupt to clear for console.\n"); 130 //panic("Need implementation\n"); 131} 132 133void 134Pc::postPciInt(int line) 135{ 136 southBridge->ioApic->signalInterrupt(line); 137} 138 139void 140Pc::clearPciInt(int line) 141{ 142 warn_once("Tried to clear PCI interrupt %d\n", line); 143} 144 145Pc * 146PcParams::create() 147{ 148 return new Pc(this); 149} 150