intdev.hh revision 9090:e4e22240398f 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2008 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __DEV_X86_INTDEV_HH__
44#define __DEV_X86_INTDEV_HH__
45
46#include <cassert>
47#include <list>
48#include <string>
49
50#include "arch/x86/intmessage.hh"
51#include "arch/x86/x86_traits.hh"
52#include "mem/mem_object.hh"
53#include "mem/mport.hh"
54#include "params/X86IntLine.hh"
55#include "params/X86IntSinkPin.hh"
56#include "params/X86IntSourcePin.hh"
57#include "sim/sim_object.hh"
58
59namespace X86ISA {
60
61typedef std::list<int> ApicList;
62
63class IntDev
64{
65  protected:
66    class IntSlavePort : public MessageSlavePort
67    {
68        IntDev * device;
69        Tick latency;
70      public:
71        IntSlavePort(const std::string& _name, MemObject* _parent,
72                     IntDev* dev, Tick _latency) :
73            MessageSlavePort(_name, _parent), device(dev), latency(_latency)
74        {
75        }
76
77        AddrRangeList getAddrRanges() const
78        {
79            return device->getIntAddrRange();
80        }
81
82        Tick recvMessage(PacketPtr pkt)
83        {
84            return device->recvMessage(pkt);
85        }
86    };
87
88    class IntMasterPort : public MessageMasterPort
89    {
90        IntDev* device;
91        Tick latency;
92      public:
93        IntMasterPort(const std::string& _name, MemObject* _parent,
94                      IntDev* dev, Tick _latency) :
95            MessageMasterPort(_name, _parent), device(dev), latency(_latency)
96        {
97        }
98
99        Tick recvResponse(PacketPtr pkt)
100        {
101            return device->recvResponse(pkt);
102        }
103
104        // This is x86 focused, so if this class becomes generic, this would
105        // need to be moved into a subclass.
106        void sendMessage(ApicList apics,
107                TriggerIntMessage message, bool timing);
108    };
109
110    IntMasterPort intMasterPort;
111
112  public:
113    IntDev(MemObject * parent, Tick latency = 0) :
114        intMasterPort(parent->name() + ".int_master", parent, this, latency)
115    {
116    }
117
118    virtual ~IntDev()
119    {}
120
121    virtual void init();
122
123    virtual void
124    signalInterrupt(int line)
125    {
126        panic("signalInterrupt not implemented.\n");
127    }
128
129    virtual void
130    raiseInterruptPin(int number)
131    {
132        panic("raiseInterruptPin not implemented.\n");
133    }
134
135    virtual void
136    lowerInterruptPin(int number)
137    {
138        panic("lowerInterruptPin not implemented.\n");
139    }
140
141    virtual Tick
142    recvMessage(PacketPtr pkt)
143    {
144        panic("recvMessage not implemented.\n");
145        return 0;
146    }
147
148    virtual Tick
149    recvResponse(PacketPtr pkt)
150    {
151        return 0;
152    }
153
154    virtual AddrRangeList
155    getIntAddrRange() const
156    {
157        panic("intAddrRange not implemented.\n");
158    }
159};
160
161class IntSinkPin : public SimObject
162{
163  public:
164    IntDev * device;
165    int number;
166
167    typedef X86IntSinkPinParams Params;
168
169    const Params *
170    params() const
171    {
172        return dynamic_cast<const Params *>(_params);
173    }
174
175    IntSinkPin(Params *p) : SimObject(p),
176            device(dynamic_cast<IntDev *>(p->device)), number(p->number)
177    {
178        assert(device);
179    }
180};
181
182class IntSourcePin : public SimObject
183{
184  protected:
185    std::vector<IntSinkPin *> sinks;
186
187  public:
188    typedef X86IntSourcePinParams Params;
189
190    const Params *
191    params() const
192    {
193        return dynamic_cast<const Params *>(_params);
194    }
195
196    void
197    addSink(IntSinkPin *sink)
198    {
199        sinks.push_back(sink);
200    }
201
202    void
203    raise()
204    {
205        for (int i = 0; i < sinks.size(); i++) {
206            const IntSinkPin &pin = *sinks[i];
207            pin.device->raiseInterruptPin(pin.number);
208        }
209    }
210
211    void
212    lower()
213    {
214        for (int i = 0; i < sinks.size(); i++) {
215            const IntSinkPin &pin = *sinks[i];
216            pin.device->lowerInterruptPin(pin.number);
217        }
218    }
219
220    IntSourcePin(Params *p) : SimObject(p)
221    {}
222};
223
224class IntLine : public SimObject
225{
226  protected:
227    IntSourcePin *source;
228    IntSinkPin *sink;
229
230  public:
231    typedef X86IntLineParams Params;
232
233    const Params *
234    params() const
235    {
236        return dynamic_cast<const Params *>(_params);
237    }
238
239    IntLine(Params *p) : SimObject(p), source(p->source), sink(p->sink)
240    {
241        source->addSink(sink);
242    }
243};
244
245} // namespace X86ISA
246
247#endif //__DEV_X86_INTDEV_HH__
248