intdev.hh revision 13892:0182a0601f66 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2008 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __DEV_X86_INTDEV_HH__
44#define __DEV_X86_INTDEV_HH__
45
46#include <cassert>
47#include <list>
48#include <string>
49
50#include "arch/x86/intmessage.hh"
51#include "arch/x86/x86_traits.hh"
52#include "mem/mport.hh"
53#include "params/X86IntLine.hh"
54#include "params/X86IntSinkPin.hh"
55#include "params/X86IntSourcePin.hh"
56#include "sim/sim_object.hh"
57
58namespace X86ISA {
59
60typedef std::list<int> ApicList;
61
62class IntDevice
63{
64  protected:
65    class IntSlavePort : public MessageSlavePort
66    {
67        IntDevice * device;
68
69      public:
70        IntSlavePort(const std::string& _name, SimObject* _parent,
71                     IntDevice* dev) :
72            MessageSlavePort(_name, _parent), device(dev)
73        {
74        }
75
76        AddrRangeList getAddrRanges() const
77        {
78            return device->getIntAddrRange();
79        }
80
81        Tick recvMessage(PacketPtr pkt)
82        {
83            // @todo someone should pay for this
84            pkt->headerDelay = pkt->payloadDelay = 0;
85            return device->recvMessage(pkt);
86        }
87    };
88
89    class IntMasterPort : public MessageMasterPort
90    {
91        IntDevice* device;
92        Tick latency;
93      public:
94        IntMasterPort(const std::string& _name, SimObject* _parent,
95                      IntDevice* dev, Tick _latency) :
96            MessageMasterPort(_name, _parent), device(dev), latency(_latency)
97        {
98        }
99
100        Tick recvResponse(PacketPtr pkt)
101        {
102            return device->recvResponse(pkt);
103        }
104
105        // This is x86 focused, so if this class becomes generic, this would
106        // need to be moved into a subclass.
107        void sendMessage(ApicList apics,
108                TriggerIntMessage message, bool timing);
109    };
110
111    IntMasterPort intMasterPort;
112
113  public:
114    IntDevice(SimObject * parent, Tick latency = 0) :
115        intMasterPort(parent->name() + ".int_master", parent, this, latency)
116    {
117    }
118
119    virtual ~IntDevice()
120    {}
121
122    virtual void init();
123
124    virtual void
125    signalInterrupt(int line)
126    {
127        panic("signalInterrupt not implemented.\n");
128    }
129
130    virtual void
131    raiseInterruptPin(int number)
132    {
133        panic("raiseInterruptPin not implemented.\n");
134    }
135
136    virtual void
137    lowerInterruptPin(int number)
138    {
139        panic("lowerInterruptPin not implemented.\n");
140    }
141
142    virtual Tick
143    recvMessage(PacketPtr pkt)
144    {
145        panic("recvMessage not implemented.\n");
146        return 0;
147    }
148
149    virtual Tick
150    recvResponse(PacketPtr pkt)
151    {
152        panic("recvResponse not implemented.\n");
153        return 0;
154    }
155
156    virtual AddrRangeList
157    getIntAddrRange() const
158    {
159        panic("intAddrRange not implemented.\n");
160    }
161};
162
163class IntSinkPin : public SimObject
164{
165  public:
166    IntDevice * device;
167    int number;
168
169    typedef X86IntSinkPinParams Params;
170
171    const Params *
172    params() const
173    {
174        return dynamic_cast<const Params *>(_params);
175    }
176
177    IntSinkPin(Params *p) : SimObject(p),
178            device(dynamic_cast<IntDevice *>(p->device)), number(p->number)
179    {
180        assert(device);
181    }
182};
183
184class IntSourcePin : public SimObject
185{
186  protected:
187    std::vector<IntSinkPin *> sinks;
188
189  public:
190    typedef X86IntSourcePinParams Params;
191
192    const Params *
193    params() const
194    {
195        return dynamic_cast<const Params *>(_params);
196    }
197
198    void
199    addSink(IntSinkPin *sink)
200    {
201        sinks.push_back(sink);
202    }
203
204    void
205    raise()
206    {
207        for (int i = 0; i < sinks.size(); i++) {
208            const IntSinkPin &pin = *sinks[i];
209            pin.device->raiseInterruptPin(pin.number);
210        }
211    }
212
213    void
214    lower()
215    {
216        for (int i = 0; i < sinks.size(); i++) {
217            const IntSinkPin &pin = *sinks[i];
218            pin.device->lowerInterruptPin(pin.number);
219        }
220    }
221
222    IntSourcePin(Params *p) : SimObject(p)
223    {}
224};
225
226class IntLine : public SimObject
227{
228  protected:
229    IntSourcePin *source;
230    IntSinkPin *sink;
231
232  public:
233    typedef X86IntLineParams Params;
234
235    const Params *
236    params() const
237    {
238        return dynamic_cast<const Params *>(_params);
239    }
240
241    IntLine(Params *p) : SimObject(p), source(p->source), sink(p->sink)
242    {
243        source->addSink(sink);
244    }
245};
246
247} // namespace X86ISA
248
249#endif //__DEV_X86_INTDEV_HH__
250