intdev.hh revision 7811 
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __DEV_X86_INTDEV_HH__
32#define __DEV_X86_INTDEV_HH__
33
34#include <cassert>
35#include <string>
36
37#include "arch/x86/x86_traits.hh"
38#include "arch/x86/intmessage.hh"
39#include "mem/mem_object.hh"
40#include "mem/mport.hh"
41#include "sim/sim_object.hh"
42#include "params/X86IntSourcePin.hh"
43#include "params/X86IntSinkPin.hh"
44#include "params/X86IntLine.hh"
45
46#include <list>
47
48namespace X86ISA {
49
50typedef std::list<int> ApicList;
51
52class IntDev
53{
54  protected:
55    class IntPort : public MessagePort
56    {
57        IntDev * device;
58        Tick latency;
59        Addr intAddr;
60      public:
61        IntPort(const std::string &_name, MemObject * _parent,
62                IntDev *dev, Tick _latency) :
63            MessagePort(_name, _parent), device(dev), latency(_latency)
64        {
65        }
66
67        void getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
68        {
69            snoop = false;
70            device->getIntAddrRange(resp);
71        }
72
73        Tick recvMessage(PacketPtr pkt)
74        {
75            return device->recvMessage(pkt);
76        }
77
78        Tick recvResponse(PacketPtr pkt)
79        {
80            return device->recvResponse(pkt);
81        }
82
83        // This is x86 focused, so if this class becomes generic, this would
84        // need to be moved into a subclass.
85        void sendMessage(ApicList apics,
86                TriggerIntMessage message, bool timing);
87
88        void recvStatusChange(Status status)
89        {
90            if (status == RangeChange) {
91                sendStatusChange(Port::RangeChange);
92            }
93        }
94
95    };
96
97    IntPort * intPort;
98
99  public:
100    IntDev(MemObject * parent, Tick latency = 0)
101    {
102        if (parent != NULL) {
103            intPort = new IntPort(parent->name() + ".int_port",
104                    parent, this, latency);
105        } else {
106            intPort = NULL;
107        }
108    }
109
110    virtual ~IntDev()
111    {}
112
113    virtual void
114    signalInterrupt(int line)
115    {
116        panic("signalInterrupt not implemented.\n");
117    }
118
119    virtual void
120    raiseInterruptPin(int number)
121    {
122        panic("raiseInterruptPin not implemented.\n");
123    }
124
125    virtual void
126    lowerInterruptPin(int number)
127    {
128        panic("lowerInterruptPin not implemented.\n");
129    }
130
131    virtual Tick
132    recvMessage(PacketPtr pkt)
133    {
134        panic("recvMessage not implemented.\n");
135        return 0;
136    }
137
138    virtual Tick
139    recvResponse(PacketPtr pkt)
140    {
141        delete pkt->req;
142        delete pkt;
143        return 0;
144    }
145
146    virtual void
147    getIntAddrRange(AddrRangeList &range_list)
148    {
149        panic("intAddrRange not implemented.\n");
150    }
151};
152
153class IntSinkPin : public SimObject
154{
155  public:
156    IntDev * device;
157    int number;
158
159    typedef X86IntSinkPinParams Params;
160
161    const Params *
162    params() const
163    {
164        return dynamic_cast<const Params *>(_params);
165    }
166
167    IntSinkPin(Params *p) : SimObject(p),
168            device(dynamic_cast<IntDev *>(p->device)), number(p->number)
169    {
170        assert(device);
171    }
172};
173
174class IntSourcePin : public SimObject
175{
176  protected:
177    std::vector<IntSinkPin *> sinks;
178
179  public:
180    typedef X86IntSourcePinParams Params;
181
182    const Params *
183    params() const
184    {
185        return dynamic_cast<const Params *>(_params);
186    }
187
188    void
189    addSink(IntSinkPin *sink)
190    {
191        sinks.push_back(sink);
192    }
193
194    void
195    raise()
196    {
197        for (int i = 0; i < sinks.size(); i++) {
198            const IntSinkPin &pin = *sinks[i];
199            pin.device->raiseInterruptPin(pin.number);
200        }
201    }
202
203    void
204    lower()
205    {
206        for (int i = 0; i < sinks.size(); i++) {
207            const IntSinkPin &pin = *sinks[i];
208            pin.device->lowerInterruptPin(pin.number);
209        }
210    }
211
212    IntSourcePin(Params *p) : SimObject(p)
213    {}
214};
215
216class IntLine : public SimObject
217{
218  protected:
219    IntSourcePin *source;
220    IntSinkPin *sink;
221
222  public:
223    typedef X86IntLineParams Params;
224
225    const Params *
226    params() const
227    {
228        return dynamic_cast<const Params *>(_params);
229    }
230
231    IntLine(Params *p) : SimObject(p), source(p->source), sink(p->sink)
232    {
233        source->addSink(sink);
234    }
235};
236
237} // namespace X86ISA
238
239#endif //__DEV_X86_INTDEV_HH__
240