intdev.cc revision 9163:3b5e13ac1940 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2008 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include "dev/x86/intdev.hh"
44
45void
46X86ISA::IntDev::IntMasterPort::sendMessage(ApicList apics,
47                                           TriggerIntMessage message,
48                                           bool timing)
49{
50    ApicList::iterator apicIt;
51    for (apicIt = apics.begin(); apicIt != apics.end(); apicIt++) {
52        PacketPtr pkt = buildIntRequest(*apicIt, message);
53        if (timing) {
54            schedTimingReq(pkt, curTick() + latency);
55            // The target handles cleaning up the packet in timing mode.
56        } else {
57            // ignore the latency involved in the atomic transaction
58            sendAtomic(pkt);
59            assert(pkt->isResponse());
60            // also ignore the latency in handling the response
61            recvResponse(pkt);
62            delete pkt->req;
63            delete pkt;
64        }
65    }
66}
67
68void
69X86ISA::IntDev::init()
70{
71    if (!intMasterPort.isConnected()) {
72        panic("Int port not connected to anything!");
73    }
74}
75
76X86ISA::IntSourcePin *
77X86IntSourcePinParams::create()
78{
79    return new X86ISA::IntSourcePin(this);
80}
81
82X86ISA::IntSinkPin *
83X86IntSinkPinParams::create()
84{
85    return new X86ISA::IntSinkPin(this);
86}
87
88X86ISA::IntLine *
89X86IntLineParams::create()
90{
91    return new X86ISA::IntLine(this);
92}
93