i8259.cc revision 5631
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "base/bitfield.hh" 32#include "dev/x86/i8259.hh" 33 34Tick 35X86ISA::I8259::read(PacketPtr pkt) 36{ 37 assert(pkt->getSize() == 1); 38 switch(pkt->getAddr() - pioAddr) 39 { 40 case 0x0: 41 if (readIRR) { 42 DPRINTF(I8259, "Reading IRR as %#x.\n", IRR); 43 pkt->set(IRR); 44 } else { 45 DPRINTF(I8259, "Reading ISR as %#x.\n", ISR); 46 pkt->set(ISR); 47 } 48 break; 49 case 0x1: 50 DPRINTF(I8259, "Reading IMR as %#x.\n", IMR); 51 pkt->set(IMR); 52 break; 53 } 54 return latency; 55} 56 57Tick 58X86ISA::I8259::write(PacketPtr pkt) 59{ 60 assert(pkt->getSize() == 1); 61 uint8_t val = pkt->get<uint8_t>(); 62 switch (pkt->getAddr() - pioAddr) { 63 case 0x0: 64 if (bits(val, 4)) { 65 DPRINTF(I8259, "Received initialization command word 1.\n"); 66 IMR = 0; 67 edgeTriggered = bits(val, 3); 68 DPRINTF(I8259, "%s triggered mode.\n", 69 edgeTriggered ? "Edge" : "Level"); 70 cascadeMode = !bits(val, 1); 71 DPRINTF(I8259, "%s mode.\n", 72 cascadeMode ? "Cascade" : "Single"); 73 expectICW4 = bits(val, 0); 74 initControlWord = 1; 75 DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2); 76 } else if (bits(val, 4, 3) == 0) { 77 DPRINTF(I8259, "Received operation command word 2.\n"); 78 switch (bits(val, 7, 5)) { 79 case 0x0: 80 DPRINTF(I8259, 81 "Subcommand: Rotate in auto-EOI mode (clear).\n"); 82 break; 83 case 0x1: 84 DPRINTF(I8259, "Subcommand: Nonspecific EOI.\n"); 85 break; 86 case 0x2: 87 DPRINTF(I8259, "Subcommand: No operation.\n"); 88 break; 89 case 0x3: 90 DPRINTF(I8259, "Subcommand: Specific EIO."); 91 DPRINTF(I8259, "Reset In-Service bit %d.\n", bits(val, 2, 0)); 92 break; 93 case 0x4: 94 DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n"); 95 break; 96 case 0x5: 97 DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n"); 98 break; 99 case 0x6: 100 DPRINTF(I8259, "Subcommand: Set priority command.\n"); 101 DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 102 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 103 break; 104 case 0x7: 105 DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n"); 106 DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 107 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 108 break; 109 } 110 } else if (bits(val, 4, 3) == 1) { 111 DPRINTF(I8259, "Received operation command word 3.\n"); 112 if (bits(val, 7)) { 113 DPRINTF(I8259, "%s special mask mode.\n", 114 bits(val, 6) ? "Set" : "Clear"); 115 } 116 if (bits(val, 1)) { 117 readIRR = bits(val, 0); 118 DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR"); 119 } 120 } 121 break; 122 case 0x1: 123 switch (initControlWord) { 124 case 0x0: 125 DPRINTF(I8259, "Received operation command word 1.\n"); 126 DPRINTF(I8259, "Wrote IMR value %#x.\n", val); 127 IMR = val; 128 break; 129 case 0x1: 130 DPRINTF(I8259, "Received initialization command word 2.\n"); 131 DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n", 132 val & ~mask(3), val | mask(3)); 133 if (cascadeMode) { 134 initControlWord++; 135 } else { 136 initControlWord = 0; 137 } 138 break; 139 case 0x2: 140 DPRINTF(I8259, "Received initialization command word 3.\n"); 141 if (master) { 142 DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n", 143 bits(val, 0) ? " 0" : "", 144 bits(val, 1) ? " 1" : "", 145 bits(val, 2) ? " 2" : "", 146 bits(val, 3) ? " 3" : "", 147 bits(val, 4) ? " 4" : "", 148 bits(val, 5) ? " 5" : "", 149 bits(val, 6) ? " 6" : "", 150 bits(val, 7) ? " 7" : ""); 151 } else { 152 DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3)); 153 } 154 if (expectICW4) 155 initControlWord++; 156 else 157 initControlWord = 0; 158 break; 159 case 0x3: 160 DPRINTF(I8259, "Received initialization command word 4.\n"); 161 if (bits(val, 4)) { 162 DPRINTF(I8259, "Special fully nested mode.\n"); 163 } else { 164 DPRINTF(I8259, "Not special fully nested mode.\n"); 165 } 166 if (bits(val, 3) == 0) { 167 DPRINTF(I8259, "Nonbuffered.\n"); 168 } else if (bits(val, 2) == 0) { 169 DPRINTF(I8259, "Buffered.\n"); 170 } else { 171 DPRINTF(I8259, "Unrecognized buffer mode.\n"); 172 } 173 DPRINTF(I8259, "%s End Of Interrupt.\n", 174 bits(val, 1) ? "Automatic" : "Normal"); 175 DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85"); 176 initControlWord = 0; 177 break; 178 } 179 break; 180 } 181 return latency; 182} 183 184X86ISA::I8259 * 185I8259Params::create() 186{ 187 return new X86ISA::I8259(this); 188} 189