i8254.cc revision 5390 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "dev/x86/south_bridge/i8254.hh"
32#include "mem/packet_access.hh"
33
34Tick
35X86ISA::I8254::read(PacketPtr pkt)
36{
37    assert(pkt->getSize() == 1);
38    switch(pkt->getAddr() - addrRange.start)
39    {
40      case 0x0:
41        warn("Reading from timer 0 counter.\n");
42        break;
43      case 0x1:
44        warn("Reading from timer 1 counter.\n");
45        break;
46      case 0x2:
47        warn("Reading from timer 2 counter.\n");
48        break;
49      case 0x3:
50        fatal("Reading from timer control word which is read only.\n");
51        break;
52      default:
53        panic("Read from undefined i8254 register.\n");
54    }
55    return SubDevice::read(pkt);
56}
57
58Tick
59X86ISA::I8254::write(PacketPtr pkt)
60{
61    assert(pkt->getSize() == 1);
62    switch(pkt->getAddr() - addrRange.start)
63    {
64      case 0x0:
65        warn("Writing to timer 0 counter.\n");
66        break;
67      case 0x1:
68        warn("Writing to timer 1 counter.\n");
69        break;
70      case 0x2:
71        warn("Writing to timer 2 counter.\n");
72        break;
73      case 0x3:
74        processControlWord(pkt->get<uint8_t>());
75        return latency;
76      default:
77        panic("Write to undefined i8254 register.\n");
78    }
79    return SubDevice::write(pkt);
80}
81
82void
83X86ISA::I8254::processControlWord(uint8_t word)
84{
85    warn("I8254 received control word %x.\n", word);
86}
87