i8254.cc revision 10905:a6ca6831e775 
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "debug/I8254.hh"
32#include "dev/x86/i8254.hh"
33#include "dev/x86/intdev.hh"
34#include "mem/packet.hh"
35#include "mem/packet_access.hh"
36
37void
38X86ISA::I8254::counterInterrupt(unsigned int num)
39{
40    DPRINTF(I8254, "Interrupt from counter %d.\n", num);
41    if (num == 0) {
42        intPin->raise();
43        //XXX This is a hack.
44        intPin->lower();
45    }
46}
47
48Tick
49X86ISA::I8254::read(PacketPtr pkt)
50{
51    assert(pkt->getSize() == 1);
52    Addr offset = pkt->getAddr() - pioAddr;
53    if (offset < 3) {
54        pkt->set(pit.readCounter(offset));
55    } else if (offset == 3) {
56        pkt->set(uint8_t(-1));
57    } else {
58        panic("Read from undefined i8254 register.\n");
59    }
60    pkt->makeAtomicResponse();
61    return latency;
62}
63
64Tick
65X86ISA::I8254::write(PacketPtr pkt)
66{
67    assert(pkt->getSize() == 1);
68    Addr offset = pkt->getAddr() - pioAddr;
69    if (offset < 3) {
70        pit.writeCounter(offset, pkt->get<uint8_t>());
71    } else if (offset == 3) {
72        pit.writeControl(pkt->get<uint8_t>());
73    } else {
74        panic("Write to undefined i8254 register.\n");
75    }
76    pkt->makeAtomicResponse();
77    return latency;
78}
79
80void
81X86ISA::I8254::serialize(CheckpointOut &cp) const
82{
83    pit.serialize("pit", cp);
84}
85
86void
87X86ISA::I8254::unserialize(CheckpointIn &cp)
88{
89    pit.unserialize("pit", cp);
90}
91
92void
93X86ISA::I8254::startup()
94{
95    pit.startup();
96}
97
98X86ISA::I8254 *
99I8254Params::create()
100{
101    return new X86ISA::I8254(this);
102}
103