i8254.cc revision 5642
15390SN/A/*
25443SN/A * Copyright (c) 2008 The Regents of The University of Michigan
35390SN/A * All rights reserved.
45390SN/A *
55390SN/A * Redistribution and use in source and binary forms, with or without
65390SN/A * modification, are permitted provided that the following conditions are
75390SN/A * met: redistributions of source code must retain the above copyright
85390SN/A * notice, this list of conditions and the following disclaimer;
95390SN/A * redistributions in binary form must reproduce the above copyright
105390SN/A * notice, this list of conditions and the following disclaimer in the
115390SN/A * documentation and/or other materials provided with the distribution;
125390SN/A * neither the name of the copyright holders nor the names of its
135390SN/A * contributors may be used to endorse or promote products derived from
145390SN/A * this software without specific prior written permission.
155390SN/A *
165390SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
175390SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
185390SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
195390SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
205390SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
215390SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
225390SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
235390SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
245390SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
255390SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
265390SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
275390SN/A *
285390SN/A * Authors: Gabe Black
295390SN/A */
305390SN/A
315636Sgblack@eecs.umich.edu#include "dev/x86/i8254.hh"
325642Sgblack@eecs.umich.edu#include "dev/x86/intdev.hh"
335636Sgblack@eecs.umich.edu#include "mem/packet.hh"
345390SN/A#include "mem/packet_access.hh"
355390SN/A
365642Sgblack@eecs.umich.eduvoid
375642Sgblack@eecs.umich.eduX86ISA::I8254::counterInterrupt(unsigned int num)
385642Sgblack@eecs.umich.edu{
395642Sgblack@eecs.umich.edu    DPRINTF(I8254, "Interrupt from counter %d.\n", num);
405642Sgblack@eecs.umich.edu    if (num == 0)
415642Sgblack@eecs.umich.edu        intPin->signalInterrupt();
425642Sgblack@eecs.umich.edu}
435642Sgblack@eecs.umich.edu
445390SN/ATick
455390SN/AX86ISA::I8254::read(PacketPtr pkt)
465390SN/A{
475390SN/A    assert(pkt->getSize() == 1);
485636Sgblack@eecs.umich.edu    Addr offset = pkt->getAddr() - pioAddr;
495636Sgblack@eecs.umich.edu    if (offset < 3) {
505636Sgblack@eecs.umich.edu        pkt->set(pit.readCounter(offset));
515636Sgblack@eecs.umich.edu    } else if (offset == 3) {
525443SN/A        pkt->set(uint8_t(-1));
535636Sgblack@eecs.umich.edu    } else {
545390SN/A        panic("Read from undefined i8254 register.\n");
555390SN/A    }
565443SN/A    return latency;
575390SN/A}
585390SN/A
595390SN/ATick
605390SN/AX86ISA::I8254::write(PacketPtr pkt)
615390SN/A{
625390SN/A    assert(pkt->getSize() == 1);
635636Sgblack@eecs.umich.edu    Addr offset = pkt->getAddr() - pioAddr;
645636Sgblack@eecs.umich.edu    if (offset < 3) {
655636Sgblack@eecs.umich.edu        pit.writeCounter(offset, pkt->get<uint8_t>());
665636Sgblack@eecs.umich.edu    } else if (offset == 3) {
675443SN/A        pit.writeControl(pkt->get<uint8_t>());
685636Sgblack@eecs.umich.edu    } else {
695390SN/A        panic("Write to undefined i8254 register.\n");
705390SN/A    }
715443SN/A    return latency;
725390SN/A}
735636Sgblack@eecs.umich.edu
745636Sgblack@eecs.umich.eduX86ISA::I8254 *
755636Sgblack@eecs.umich.eduI8254Params::create()
765636Sgblack@eecs.umich.edu{
775636Sgblack@eecs.umich.edu    return new X86ISA::I8254(this);
785636Sgblack@eecs.umich.edu}
79