i8254.cc revision 5443
111527Sdavid.guillen@arm.com/* 211967Sandreas.sandberg@arm.com * Copyright (c) 2008 The Regents of The University of Michigan 311527Sdavid.guillen@arm.com * All rights reserved. 411527Sdavid.guillen@arm.com * 511527Sdavid.guillen@arm.com * Redistribution and use in source and binary forms, with or without 611527Sdavid.guillen@arm.com * modification, are permitted provided that the following conditions are 711527Sdavid.guillen@arm.com * met: redistributions of source code must retain the above copyright 811527Sdavid.guillen@arm.com * notice, this list of conditions and the following disclaimer; 911527Sdavid.guillen@arm.com * redistributions in binary form must reproduce the above copyright 1011527Sdavid.guillen@arm.com * notice, this list of conditions and the following disclaimer in the 1111527Sdavid.guillen@arm.com * documentation and/or other materials provided with the distribution; 1211527Sdavid.guillen@arm.com * neither the name of the copyright holders nor the names of its 1311527Sdavid.guillen@arm.com * contributors may be used to endorse or promote products derived from 1411527Sdavid.guillen@arm.com * this software without specific prior written permission. 1511527Sdavid.guillen@arm.com * 1611527Sdavid.guillen@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711527Sdavid.guillen@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811527Sdavid.guillen@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911527Sdavid.guillen@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011527Sdavid.guillen@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111527Sdavid.guillen@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211527Sdavid.guillen@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311527Sdavid.guillen@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411527Sdavid.guillen@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511527Sdavid.guillen@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611527Sdavid.guillen@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711527Sdavid.guillen@arm.com * 2811527Sdavid.guillen@arm.com * Authors: Gabe Black 2911527Sdavid.guillen@arm.com */ 3011527Sdavid.guillen@arm.com 3111527Sdavid.guillen@arm.com#include "dev/x86/south_bridge/i8254.hh" 3211527Sdavid.guillen@arm.com#include "mem/packet_access.hh" 3311527Sdavid.guillen@arm.com 3411527Sdavid.guillen@arm.comTick 3511527Sdavid.guillen@arm.comX86ISA::I8254::read(PacketPtr pkt) 3611527Sdavid.guillen@arm.com{ 3711527Sdavid.guillen@arm.com assert(pkt->getSize() == 1); 3811527Sdavid.guillen@arm.com switch(pkt->getAddr() - addrRange.start) 3911527Sdavid.guillen@arm.com { 4011527Sdavid.guillen@arm.com case 0x0: 4111527Sdavid.guillen@arm.com pkt->set(pit.counter0.read()); 4211527Sdavid.guillen@arm.com break; 4311527Sdavid.guillen@arm.com case 0x1: 4411527Sdavid.guillen@arm.com pkt->set(pit.counter1.read()); 4511527Sdavid.guillen@arm.com break; 4611527Sdavid.guillen@arm.com case 0x2: 4711527Sdavid.guillen@arm.com pkt->set(pit.counter2.read()); 4811527Sdavid.guillen@arm.com break; 4911967Sandreas.sandberg@arm.com case 0x3: 5011527Sdavid.guillen@arm.com pkt->set(uint8_t(-1)); 5111527Sdavid.guillen@arm.com break; 5211527Sdavid.guillen@arm.com default: 5311527Sdavid.guillen@arm.com panic("Read from undefined i8254 register.\n"); 5411527Sdavid.guillen@arm.com } 5511527Sdavid.guillen@arm.com return latency; 5611527Sdavid.guillen@arm.com} 5711527Sdavid.guillen@arm.com 5811527Sdavid.guillen@arm.comTick 5911527Sdavid.guillen@arm.comX86ISA::I8254::write(PacketPtr pkt) 6011527Sdavid.guillen@arm.com{ 6111527Sdavid.guillen@arm.com assert(pkt->getSize() == 1); 6211527Sdavid.guillen@arm.com switch(pkt->getAddr() - addrRange.start) 6311527Sdavid.guillen@arm.com { 6411527Sdavid.guillen@arm.com case 0x0: 6511527Sdavid.guillen@arm.com pit.counter0.write(pkt->get<uint8_t>()); 6611527Sdavid.guillen@arm.com break; 6711527Sdavid.guillen@arm.com case 0x1: 6811967Sandreas.sandberg@arm.com pit.counter1.write(pkt->get<uint8_t>()); 6911967Sandreas.sandberg@arm.com break; 7011967Sandreas.sandberg@arm.com case 0x2: 7111967Sandreas.sandberg@arm.com pit.counter2.write(pkt->get<uint8_t>()); 7211967Sandreas.sandberg@arm.com break; 7311967Sandreas.sandberg@arm.com case 0x3: 7411967Sandreas.sandberg@arm.com pit.writeControl(pkt->get<uint8_t>()); 7511967Sandreas.sandberg@arm.com break; 7611967Sandreas.sandberg@arm.com default: 7711967Sandreas.sandberg@arm.com panic("Write to undefined i8254 register.\n"); 7811967Sandreas.sandberg@arm.com } 7911967Sandreas.sandberg@arm.com return latency; 8011967Sandreas.sandberg@arm.com} 8111967Sandreas.sandberg@arm.com