i8254.cc revision 14290
17405SAli.Saidi@ARM.com/* 211573SDylan.Johnson@ARM.com * Copyright (c) 2008 The Regents of The University of Michigan 37405SAli.Saidi@ARM.com * All rights reserved. 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 147405SAli.Saidi@ARM.com * this software without specific prior written permission. 157405SAli.Saidi@ARM.com * 167405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277405SAli.Saidi@ARM.com * 287405SAli.Saidi@ARM.com * Authors: Gabe Black 297405SAli.Saidi@ARM.com */ 307405SAli.Saidi@ARM.com 317405SAli.Saidi@ARM.com#include "dev/x86/i8254.hh" 327405SAli.Saidi@ARM.com 337405SAli.Saidi@ARM.com#include "debug/I8254.hh" 347405SAli.Saidi@ARM.com#include "dev/x86/intdev.hh" 357405SAli.Saidi@ARM.com#include "mem/packet.hh" 367405SAli.Saidi@ARM.com#include "mem/packet_access.hh" 377405SAli.Saidi@ARM.com 387405SAli.Saidi@ARM.comvoid 397405SAli.Saidi@ARM.comX86ISA::I8254::counterInterrupt(unsigned int num) 407405SAli.Saidi@ARM.com{ 417405SAli.Saidi@ARM.com DPRINTF(I8254, "Interrupt from counter %d.\n", num); 4210461SAndreas.Sandberg@ARM.com if (num == 0) { 439050Schander.sudanthi@arm.com for (auto *wire: intPin) { 448887Sgeoffrey.blake@arm.com wire->raise(); 4510461SAndreas.Sandberg@ARM.com //XXX This is a hack. 468232Snate@binkert.org wire->lower(); 478232Snate@binkert.org } 4810844Sandreas.sandberg@arm.com } 499384SAndreas.Sandberg@arm.com} 507678Sgblack@eecs.umich.edu 518059SAli.Saidi@ARM.comTick 528284SAli.Saidi@ARM.comX86ISA::I8254::read(PacketPtr pkt) 537405SAli.Saidi@ARM.com{ 547405SAli.Saidi@ARM.com assert(pkt->getSize() == 1); 557405SAli.Saidi@ARM.com Addr offset = pkt->getAddr() - pioAddr; 567405SAli.Saidi@ARM.com if (offset < 3) { 5710037SARM gem5 Developers pkt->setLE(pit.readCounter(offset)); 5810037SARM gem5 Developers } else if (offset == 3) { 5910037SARM gem5 Developers pkt->setLE(uint8_t(-1)); 6010037SARM gem5 Developers } else { 6110037SARM gem5 Developers panic("Read from undefined i8254 register.\n"); 6210037SARM gem5 Developers } 6310037SARM gem5 Developers pkt->makeAtomicResponse(); 6410037SARM gem5 Developers return latency; 6510037SARM gem5 Developers} 6610037SARM gem5 Developers 6710037SARM gem5 DevelopersTick 6810037SARM gem5 DevelopersX86ISA::I8254::write(PacketPtr pkt) 6910037SARM gem5 Developers{ 7010037SARM gem5 Developers assert(pkt->getSize() == 1); 7110037SARM gem5 Developers Addr offset = pkt->getAddr() - pioAddr; 7210037SARM gem5 Developers if (offset < 3) { 7310037SARM gem5 Developers pit.writeCounter(offset, pkt->getLE<uint8_t>()); 7410037SARM gem5 Developers } else if (offset == 3) { 7510037SARM gem5 Developers pit.writeControl(pkt->getLE<uint8_t>()); 7610037SARM gem5 Developers } else { 7710037SARM gem5 Developers panic("Write to undefined i8254 register.\n"); 7810037SARM gem5 Developers } 7910037SARM gem5 Developers pkt->makeAtomicResponse(); 8010037SARM gem5 Developers return latency; 8110037SARM gem5 Developers} 8210037SARM gem5 Developers 8310037SARM gem5 Developersvoid 8410037SARM gem5 DevelopersX86ISA::I8254::serialize(CheckpointOut &cp) const 8510037SARM gem5 Developers{ 8610037SARM gem5 Developers pit.serialize("pit", cp); 8710037SARM gem5 Developers} 8810037SARM gem5 Developers 8910037SARM gem5 Developersvoid 9010037SARM gem5 DevelopersX86ISA::I8254::unserialize(CheckpointIn &cp) 9110037SARM gem5 Developers{ 9210037SARM gem5 Developers pit.unserialize("pit", cp); 9310037SARM gem5 Developers} 9410037SARM gem5 Developers 9510037SARM gem5 Developersvoid 9610037SARM gem5 DevelopersX86ISA::I8254::startup() 9710037SARM gem5 Developers{ 9810037SARM gem5 Developers pit.startup(); 9910037SARM gem5 Developers} 10010037SARM gem5 Developers 10110037SARM gem5 DevelopersX86ISA::I8254 * 10210037SARM gem5 DevelopersI8254Params::create() 10310037SARM gem5 Developers{ 10410037SARM gem5 Developers return new X86ISA::I8254(this); 10510037SARM gem5 Developers} 10610037SARM gem5 Developers