i8254.cc revision 10642
17405SAli.Saidi@ARM.com/* 212667Schuan.zhu@arm.com * Copyright (c) 2008 The Regents of The University of Michigan 37405SAli.Saidi@ARM.com * All rights reserved. 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 147405SAli.Saidi@ARM.com * this software without specific prior written permission. 157405SAli.Saidi@ARM.com * 167405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277405SAli.Saidi@ARM.com * 287405SAli.Saidi@ARM.com * Authors: Gabe Black 297405SAli.Saidi@ARM.com */ 307405SAli.Saidi@ARM.com 317405SAli.Saidi@ARM.com#include "debug/I8254.hh" 327405SAli.Saidi@ARM.com#include "dev/x86/i8254.hh" 337405SAli.Saidi@ARM.com#include "dev/x86/intdev.hh" 347405SAli.Saidi@ARM.com#include "mem/packet.hh" 357405SAli.Saidi@ARM.com#include "mem/packet_access.hh" 367405SAli.Saidi@ARM.com 377405SAli.Saidi@ARM.comvoid 387405SAli.Saidi@ARM.comX86ISA::I8254::counterInterrupt(unsigned int num) 397405SAli.Saidi@ARM.com{ 407405SAli.Saidi@ARM.com DPRINTF(I8254, "Interrupt from counter %d.\n", num); 417405SAli.Saidi@ARM.com if (num == 0) { 4210461SAndreas.Sandberg@ARM.com intPin->raise(); 439050Schander.sudanthi@arm.com //XXX This is a hack. 4412406Sgabeblack@google.com intPin->lower(); 4512605Sgiacomo.travaglini@arm.com } 4611793Sbrandon.potter@amd.com} 478887Sgeoffrey.blake@arm.com 488232Snate@binkert.orgTick 498232Snate@binkert.orgX86ISA::I8254::read(PacketPtr pkt) 5010844Sandreas.sandberg@arm.com{ 519384SAndreas.Sandberg@arm.com assert(pkt->getSize() == 1); 527678Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 538059SAli.Saidi@ARM.com if (offset < 3) { 548284SAli.Saidi@ARM.com pkt->set(pit.readCounter(offset)); 557405SAli.Saidi@ARM.com } else if (offset == 3) { 567405SAli.Saidi@ARM.com pkt->set(uint8_t(-1)); 577405SAli.Saidi@ARM.com } else { 587405SAli.Saidi@ARM.com panic("Read from undefined i8254 register.\n"); 599384SAndreas.Sandberg@arm.com } 6010461SAndreas.Sandberg@ARM.com pkt->makeAtomicResponse(); 6110461SAndreas.Sandberg@ARM.com return latency; 6211165SRekai.GonzalezAlberquilla@arm.com} 6312109SRekai.GonzalezAlberquilla@arm.com 6412479SCurtis.Dunham@arm.comTick 659384SAndreas.Sandberg@arm.comX86ISA::I8254::write(PacketPtr pkt) 6611770SCurtis.Dunham@arm.com{ 6710037SARM gem5 Developers assert(pkt->getSize() == 1); 6810461SAndreas.Sandberg@ARM.com Addr offset = pkt->getAddr() - pioAddr; 6910461SAndreas.Sandberg@ARM.com if (offset < 3) { 7010461SAndreas.Sandberg@ARM.com pit.writeCounter(offset, pkt->get<uint8_t>()); 7110461SAndreas.Sandberg@ARM.com } else if (offset == 3) { 7210461SAndreas.Sandberg@ARM.com pit.writeControl(pkt->get<uint8_t>()); 7310461SAndreas.Sandberg@ARM.com } else { 7410609Sandreas.sandberg@arm.com panic("Write to undefined i8254 register.\n"); 7510609Sandreas.sandberg@arm.com } 7610609Sandreas.sandberg@arm.com pkt->makeAtomicResponse(); 7710037SARM gem5 Developers return latency; 7810037SARM gem5 Developers} 7910037SARM gem5 Developers 8010037SARM gem5 Developersvoid 8111771SCurtis.Dunham@arm.comX86ISA::I8254::serialize(std::ostream &os) 8210037SARM gem5 Developers{ 8310037SARM gem5 Developers pit.serialize("pit", os); 8410037SARM gem5 Developers} 8510037SARM gem5 Developers 8610037SARM gem5 Developersvoid 8710037SARM gem5 DevelopersX86ISA::I8254::unserialize(Checkpoint *cp, const std::string §ion) 8811771SCurtis.Dunham@arm.com{ 8910037SARM gem5 Developers pit.unserialize("pit", cp, section); 9010037SARM gem5 Developers} 9110037SARM gem5 Developers 9210037SARM gem5 Developersvoid 9310037SARM gem5 DevelopersX86ISA::I8254::startup() 9412477SCurtis.Dunham@arm.com{ 9510037SARM gem5 Developers pit.startup(); 9610037SARM gem5 Developers} 979384SAndreas.Sandberg@arm.com 989384SAndreas.Sandberg@arm.comX86ISA::I8254 * 999384SAndreas.Sandberg@arm.comI8254Params::create() 10012479SCurtis.Dunham@arm.com{ 10112479SCurtis.Dunham@arm.com return new X86ISA::I8254(this); 1029384SAndreas.Sandberg@arm.com} 1039384SAndreas.Sandberg@arm.com