i82094aa.hh revision 5827:ac2c268bf4f1
16019Shines@cs.fsu.edu/* 210037SARM gem5 Developers * Copyright (c) 2008 The Regents of The University of Michigan 310037SARM gem5 Developers * All rights reserved. 410037SARM gem5 Developers * 510037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 610037SARM gem5 Developers * modification, are permitted provided that the following conditions are 710037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 810037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 910037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1010037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 1110037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 1210037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 1310037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * Authors: Gabe Black 296019Shines@cs.fsu.edu */ 306019Shines@cs.fsu.edu 316019Shines@cs.fsu.edu#ifndef __DEV_X86_I82094AA_HH__ 326019Shines@cs.fsu.edu#define __DEV_X86_I82094AA_HH__ 336019Shines@cs.fsu.edu 346019Shines@cs.fsu.edu#include "base/bitunion.hh" 356019Shines@cs.fsu.edu#include "base/range_map.hh" 366019Shines@cs.fsu.edu#include "dev/io_device.hh" 376019Shines@cs.fsu.edu#include "dev/x86/intdev.hh" 386019Shines@cs.fsu.edu#include "params/I82094AA.hh" 396019Shines@cs.fsu.edu 406019Shines@cs.fsu.edunamespace X86ISA 416019Shines@cs.fsu.edu{ 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.educlass I8259; 4411383Sbrandon.potter@amd.com 4511383Sbrandon.potter@amd.comclass I82094AA : public PioDevice, public IntDev 468229Snate@binkert.org{ 4711383Sbrandon.potter@amd.com public: 486019Shines@cs.fsu.edu BitUnion64(RedirTableEntry) 496019Shines@cs.fsu.edu Bitfield<63, 32> topDW; 5011381Sbrandon.potter@amd.com Bitfield<55, 32> topReserved; 516019Shines@cs.fsu.edu Bitfield<31, 0> bottomDW; 5210037SARM gem5 Developers Bitfield<31, 17> bottomReserved; 5310037SARM gem5 Developers Bitfield<63, 56> dest; 5410037SARM gem5 Developers Bitfield<16> mask; 5511382Sbrandon.potter@amd.com Bitfield<15> trigger; 5611382Sbrandon.potter@amd.com Bitfield<14> remoteIRR; 5711382Sbrandon.potter@amd.com Bitfield<13> polarity; 5811382Sbrandon.potter@amd.com Bitfield<12> deliveryStatus; 5911382Sbrandon.potter@amd.com Bitfield<11> destMode; 6011382Sbrandon.potter@amd.com Bitfield<10, 8> deliveryMode; 6110037SARM gem5 Developers Bitfield<7, 0> vector; 626019Shines@cs.fsu.edu EndBitUnion(RedirTableEntry) 6310037SARM gem5 Developers 646019Shines@cs.fsu.edu protected: 6511382Sbrandon.potter@amd.com Tick latency; 6611382Sbrandon.potter@amd.com Addr pioAddr; 6711382Sbrandon.potter@amd.com 6811382Sbrandon.potter@amd.com I8259 * extIntPic; 6911382Sbrandon.potter@amd.com 7011382Sbrandon.potter@amd.com uint8_t regSel; 7111382Sbrandon.potter@amd.com uint8_t id; 7211382Sbrandon.potter@amd.com uint8_t arbId; 7311382Sbrandon.potter@amd.com 7411382Sbrandon.potter@amd.com static const uint8_t TableSize = 24; 7511382Sbrandon.potter@amd.com // This implementation is based on version 0x11, but 0x14 avoids having 766019Shines@cs.fsu.edu // to deal with the arbitration and APIC bus guck. 776019Shines@cs.fsu.edu static const uint8_t APICVersion = 0x14; 7810037SARM gem5 Developers 796019Shines@cs.fsu.edu RedirTableEntry redirTable[TableSize]; 8011382Sbrandon.potter@amd.com bool pinStates[TableSize]; 8111382Sbrandon.potter@amd.com 8211382Sbrandon.potter@amd.com public: 836019Shines@cs.fsu.edu typedef I82094AAParams Params; 8410037SARM gem5 Developers 8510037SARM gem5 Developers const Params * 8610037SARM gem5 Developers params() const 8710037SARM gem5 Developers { 8810037SARM gem5 Developers return dynamic_cast<const Params *>(_params); 8910037SARM gem5 Developers } 9010037SARM gem5 Developers 9110037SARM gem5 Developers I82094AA(Params *p); 9210037SARM gem5 Developers 9311382Sbrandon.potter@amd.com Tick read(PacketPtr pkt); 9411382Sbrandon.potter@amd.com Tick write(PacketPtr pkt); 956019Shines@cs.fsu.edu 9611382Sbrandon.potter@amd.com void addressRanges(AddrRangeList &range_list) 977441SAli.Saidi@ARM.com { 9810037SARM gem5 Developers range_list.clear(); 997441SAli.Saidi@ARM.com range_list.push_back(RangeEx(pioAddr, pioAddr + 4)); 1007441SAli.Saidi@ARM.com range_list.push_back(RangeEx(pioAddr + 16, pioAddr + 20)); 10110037SARM gem5 Developers } 1027441SAli.Saidi@ARM.com 1037441SAli.Saidi@ARM.com void getIntAddrRange(AddrRangeList &range_list) 10410037SARM gem5 Developers { 1057441SAli.Saidi@ARM.com range_list.clear(); 1067441SAli.Saidi@ARM.com range_list.push_back(RangeEx(x86InterruptAddress(1, 0), 10710037SARM gem5 Developers x86InterruptAddress(1, 0) + PhysAddrAPICRangeSize)); 1087441SAli.Saidi@ARM.com } 10911382Sbrandon.potter@amd.com 11011382Sbrandon.potter@amd.com void writeReg(uint8_t offset, uint32_t value); 11111382Sbrandon.potter@amd.com uint32_t readReg(uint8_t offset); 11211382Sbrandon.potter@amd.com 11311382Sbrandon.potter@amd.com Port *getPort(const std::string &if_name, int idx = -1) 11411382Sbrandon.potter@amd.com { 11511382Sbrandon.potter@amd.com if (if_name == "int_port") 11611382Sbrandon.potter@amd.com return intPort; 11711382Sbrandon.potter@amd.com return PioDevice::getPort(if_name, idx); 11811382Sbrandon.potter@amd.com } 1196019Shines@cs.fsu.edu 1206019Shines@cs.fsu.edu void signalInterrupt(int line); 1216019Shines@cs.fsu.edu void raiseInterruptPin(int number); 12210037SARM gem5 Developers void lowerInterruptPin(int number); 12310037SARM gem5 Developers}; 1246019Shines@cs.fsu.edu 12511383Sbrandon.potter@amd.com}; // namespace X86ISA 12611383Sbrandon.potter@amd.com 12711383Sbrandon.potter@amd.com#endif //__DEV_X86_SOUTH_BRIDGE_I8254_HH__ 12811383Sbrandon.potter@amd.com