cmos.hh revision 5393
12497SN/A/* 210719SMarco.Balboni@ARM.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 38711SN/A * All rights reserved. 48711SN/A * 58711SN/A * Redistribution and use in source and binary forms, with or without 68711SN/A * modification, are permitted provided that the following conditions are 78711SN/A * met: redistributions of source code must retain the above copyright 88711SN/A * notice, this list of conditions and the following disclaimer; 98711SN/A * redistributions in binary form must reproduce the above copyright 108711SN/A * notice, this list of conditions and the following disclaimer in the 118711SN/A * documentation and/or other materials provided with the distribution; 128711SN/A * neither the name of the copyright holders nor the names of its 138711SN/A * contributors may be used to endorse or promote products derived from 142497SN/A * this software without specific prior written permission. 152497SN/A * 162497SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172497SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182497SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192497SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202497SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212497SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222497SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232497SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242497SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252497SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262497SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272497SN/A * 282497SN/A * Authors: Gabe Black 292497SN/A */ 302497SN/A 312497SN/A#ifndef __DEV_X86_SOUTH_BRIDGE_CMOS_HH__ 322497SN/A#define __DEV_X86_SOUTH_BRIDGE_CMOS_HH__ 332497SN/A 342497SN/A#include "arch/x86/x86_traits.hh" 352497SN/A#include "base/range.hh" 362497SN/A#include "dev/mc146818.hh" 372497SN/A#include "dev/x86/south_bridge/sub_device.hh" 382497SN/A 392665SN/Anamespace X86ISA 402665SN/A{ 418715SN/A 428922SN/Aclass Cmos : public SubDevice 432497SN/A{ 442497SN/A protected: 452497SN/A uint8_t address; 462982SN/A 4710405Sandreas.hansson@arm.com struct tm foo_time; 482497SN/A 492497SN/A static const int numRegs = 128; 502846SN/A 512548SN/A uint8_t regs[numRegs]; 5210405Sandreas.hansson@arm.com 5310405Sandreas.hansson@arm.com uint8_t readRegister(uint8_t reg); 5410405Sandreas.hansson@arm.com void writeRegister(uint8_t reg, uint8_t val); 559524SN/A 562497SN/A class X86RTC : public MC146818 5710405Sandreas.hansson@arm.com { 5810719SMarco.Balboni@ARM.com public: 5910719SMarco.Balboni@ARM.com X86RTC(const std::string &n, const struct tm time, 607523SN/A bool bcd, Tick frequency) : MC146818(n, time, bcd, frequency) 618851SN/A { 628948SN/A } 638948SN/A protected: 648851SN/A void handleEvent() 659095SN/A { 6610405Sandreas.hansson@arm.com return; 678922SN/A } 689715SN/A } rtc; 699715SN/A 7010713Sandreas.hansson@arm.com public: 7110713Sandreas.hansson@arm.com 728851SN/A Cmos() : rtc("rtc", foo_time, true, 5000000000) 738851SN/A { 748948SN/A memset(regs, 0, numRegs * sizeof(uint8_t)); 758948SN/A address = 0; 768915SN/A } 779031SN/A 789095SN/A Cmos(Tick _latency) : SubDevice(_latency), 7910405Sandreas.hansson@arm.com rtc("rtc", foo_time, true, 5000000000) 809036SN/A { 818922SN/A memset(regs, 0, numRegs * sizeof(uint8_t)); 829715SN/A address = 0; 839715SN/A } 8410713Sandreas.hansson@arm.com 8510713Sandreas.hansson@arm.com Cmos(Addr start, Addr size, Tick _latency) : 8610713Sandreas.hansson@arm.com SubDevice(start, size, _latency), 878915SN/A rtc("rtc", foo_time, true, 5000000000) 888915SN/A { 898948SN/A memset(regs, 0, numRegs * sizeof(uint8_t)); 908851SN/A address = 0; 919095SN/A } 9210888Sandreas.hansson@arm.com 938922SN/A Tick read(PacketPtr pkt); 949715SN/A 959715SN/A Tick write(PacketPtr pkt); 969716SN/A}; 978851SN/A 988851SN/A}; // namespace X86ISA 9910402SN/A 10010402SN/A#endif //__DEV_X86_SOUTH_BRIDGE_CMOS_HH__ 10110402SN/A