SouthBridge.py revision 5827
1# Copyright (c) 2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Gabe Black 28 29from m5.params import * 30from m5.proxy import * 31from Cmos import Cmos 32from I82094AA import I82094AA 33from I8237 import I8237 34from I8254 import I8254 35from I8259 import I8259 36from PcSpeaker import PcSpeaker 37from X86IntPin import X86IntLine 38from m5.SimObject import SimObject 39 40def x86IOAddress(port): 41 IO_address_space_base = 0x8000000000000000 42 return IO_address_space_base + port; 43 44class SouthBridge(SimObject): 45 type = 'SouthBridge' 46 pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") 47 platform = Param.Platform(Parent.any, "Platform this device is part of") 48 49 _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master') 50 _pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave') 51 _cmos = Cmos(pio_addr=x86IOAddress(0x70)) 52 _dma1 = I8237(pio_addr=x86IOAddress(0x0)) 53 _pit = I8254(pio_addr=x86IOAddress(0x40)) 54 _speaker = PcSpeaker(pio_addr=x86IOAddress(0x61)) 55 _io_apic = I82094AA(pio_addr=0xFEC00000) 56 # This is to make sure the interrupt lines are instantiated. Don't use 57 # it for anything directly. 58 int_lines = VectorParam.X86IntLine([], "Interrupt lines") 59 60 pic1 = Param.I8259(_pic1, "Master PIC") 61 pic2 = Param.I8259(_pic2, "Slave PIC") 62 cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device") 63 dma1 = Param.I8237(_dma1, "The first dma controller") 64 pit = Param.I8254(_pit, "Programmable interval timer") 65 speaker = Param.PcSpeaker(_speaker, "PC speaker") 66 io_apic = Param.I82094AA(_io_apic, "I/O APIC") 67 68 def connectPins(self, source, sink): 69 self.int_lines.append(X86IntLine(source=source, sink=sink)) 70 71 def attachIO(self, bus): 72 # Route interupt signals 73 self.connectPins(self.pic1.output, self.io_apic.pin(0)) 74 self.connectPins(self.pic2.output, self.pic1.pin(2)) 75 self.connectPins(self.cmos.int_pin, self.pic2.pin(0)) 76 self.connectPins(self.pit.int_pin, self.pic1.pin(0)) 77 self.connectPins(self.pit.int_pin, self.io_apic.pin(2)) 78 # Tell the devices about each other 79 self.pic1.slave = self.pic2 80 self.speaker.i8254 = self.pit 81 self.io_apic.external_int_pic = self.pic1 82 # Connect to the bus 83 self.cmos.pio = bus.port 84 self.dma1.pio = bus.port 85 self.pic1.pio = bus.port 86 self.pic2.pio = bus.port 87 self.pit.pio = bus.port 88 self.speaker.pio = bus.port 89 self.io_apic.pio = bus.port 90 self.io_apic.int_port = bus.port 91