SouthBridge.py revision 13665:9c7fe3811b88
15369Ssaidi@eecs.umich.edu# Copyright (c) 2008 The Regents of The University of Michigan 23005Sstever@eecs.umich.edu# All rights reserved. 33005Sstever@eecs.umich.edu# 43005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 53005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 63005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 73005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 83005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 93005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 103005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 113005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 123005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 133005Sstever@eecs.umich.edu# this software without specific prior written permission. 143005Sstever@eecs.umich.edu# 153005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263005Sstever@eecs.umich.edu# 273005Sstever@eecs.umich.edu# Authors: Gabe Black 283005Sstever@eecs.umich.edu 292710SN/Afrom m5.params import * 302710SN/Afrom m5.proxy import * 313005Sstever@eecs.umich.edufrom m5.objects.Cmos import Cmos 322889SN/Afrom m5.objects.I8042 import I8042 336654Snate@binkert.orgfrom m5.objects.I82094AA import I82094AA 346654Snate@binkert.orgfrom m5.objects.I8237 import I8237 356654Snate@binkert.orgfrom m5.objects.I8254 import I8254 366654Snate@binkert.orgfrom m5.objects.I8259 import I8259 376654Snate@binkert.orgfrom m5.objects.Ide import IdeController 382667SN/Afrom m5.objects.PcSpeaker import PcSpeaker 396654Snate@binkert.orgfrom m5.objects.X86IntPin import X86IntLine 406654Snate@binkert.orgfrom m5.SimObject import SimObject 416654Snate@binkert.org 425457Ssaidi@eecs.umich.edudef x86IOAddress(port): 436654Snate@binkert.org IO_address_space_base = 0x8000000000000000 446654Snate@binkert.org return IO_address_space_base + port; 455457Ssaidi@eecs.umich.edu 466654Snate@binkert.orgclass SouthBridge(SimObject): 476654Snate@binkert.org type = 'SouthBridge' 483395Shsul@eecs.umich.edu cxx_header = "dev/x86/south_bridge.hh" 496981SLisa.Hsu@amd.com platform = Param.Platform(Parent.any, "Platform this device is part of") 503448Shsul@eecs.umich.edu 515369Ssaidi@eecs.umich.edu _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master') 523394Shsul@eecs.umich.edu _pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave') 533444Sktlim@umich.edu _cmos = Cmos(pio_addr=x86IOAddress(0x70)) 543444Sktlim@umich.edu _dma1 = I8237(pio_addr=x86IOAddress(0x0)) 553444Sktlim@umich.edu _keyboard = I8042(data_port=x86IOAddress(0x60), \ 563444Sktlim@umich.edu command_port=x86IOAddress(0x64)) 572424SN/A _pit = I8254(pio_addr=x86IOAddress(0x40)) 582957SN/A _speaker = PcSpeaker(pio_addr=x86IOAddress(0x61)) 592957SN/A _io_apic = I82094AA(pio_addr=0xFEC00000) 603323Shsul@eecs.umich.edu 613005Sstever@eecs.umich.edu pic1 = Param.I8259(_pic1, "Master PIC") 627787SAli.Saidi@ARM.com pic2 = Param.I8259(_pic2, "Slave PIC") 637787SAli.Saidi@ARM.com cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device") 645514SMichael.Adler@intel.com dma1 = Param.I8237(_dma1, "The first dma controller") 652957SN/A keyboard = Param.I8042(_keyboard, "The keyboard controller") 665514SMichael.Adler@intel.com pit = Param.I8254(_pit, "Programmable interval timer") 675514SMichael.Adler@intel.com speaker = Param.PcSpeaker(_speaker, "PC speaker") 685514SMichael.Adler@intel.com io_apic = Param.I82094AA(_io_apic, "I/O APIC") 695514SMichael.Adler@intel.com 703323Shsul@eecs.umich.edu # IDE controller 713444Sktlim@umich.edu ide = IdeController(disks=[], pci_func=0, pci_dev=4, pci_bus=0) 722957SN/A ide.BAR0 = 0x1f0 732957SN/A ide.BAR0LegacyIO = True 742957SN/A ide.BAR1 = 0x3f4 752957SN/A ide.BAR1Size = '3B' 762957SN/A ide.BAR1LegacyIO = True 772957SN/A ide.BAR2 = 0x170 782957SN/A ide.BAR2LegacyIO = True 798167SLisa.Hsu@amd.com ide.BAR3 = 0x374 808167SLisa.Hsu@amd.com ide.BAR3Size = '3B' 818167SLisa.Hsu@amd.com ide.BAR3LegacyIO = True 825369Ssaidi@eecs.umich.edu ide.BAR4 = 1 838167SLisa.Hsu@amd.com ide.Command = 0 848167SLisa.Hsu@amd.com ide.ProgIF = 0x80 858167SLisa.Hsu@amd.com ide.InterruptLine = 14 868167SLisa.Hsu@amd.com ide.InterruptPin = 1 878167SLisa.Hsu@amd.com ide.LegacyIOBase = x86IOAddress(0) 888167SLisa.Hsu@amd.com 898167SLisa.Hsu@amd.com def attachIO(self, bus, dma_ports): 908168SLisa.Hsu@amd.com # Route interupt signals 918168SLisa.Hsu@amd.com self.int_lines = \ 928168SLisa.Hsu@amd.com [X86IntLine(source=self.pic1.output, sink=self.io_apic.pin(0)), 938168SLisa.Hsu@amd.com X86IntLine(source=self.pic2.output, sink=self.pic1.pin(2)), 948167SLisa.Hsu@amd.com X86IntLine(source=self.cmos.int_pin, sink=self.pic2.pin(0)), 958167SLisa.Hsu@amd.com X86IntLine(source=self.pit.int_pin, sink=self.pic1.pin(0)), 968168SLisa.Hsu@amd.com X86IntLine(source=self.pit.int_pin, sink=self.io_apic.pin(2)), 975369Ssaidi@eecs.umich.edu X86IntLine(source=self.keyboard.keyboard_int_pin, 985369Ssaidi@eecs.umich.edu sink=self.io_apic.pin(1)), 995369Ssaidi@eecs.umich.edu X86IntLine(source=self.keyboard.mouse_int_pin, 1005369Ssaidi@eecs.umich.edu sink=self.io_apic.pin(12))] 1015369Ssaidi@eecs.umich.edu # Tell the devices about each other 1028167SLisa.Hsu@amd.com self.pic1.slave = self.pic2 1035369Ssaidi@eecs.umich.edu self.speaker.i8254 = self.pit 1045369Ssaidi@eecs.umich.edu self.io_apic.external_int_pic = self.pic1 1052801SN/A # Connect to the bus 1062801SN/A self.cmos.pio = bus.master 1075514SMichael.Adler@intel.com self.dma1.pio = bus.master 1085514SMichael.Adler@intel.com self.ide.pio = bus.master 1095514SMichael.Adler@intel.com if dma_ports.count(self.ide.dma) == 0: 1105514SMichael.Adler@intel.com self.ide.dma = bus.slave 1112418SN/A self.keyboard.pio = bus.master 1126391Sksewell@umich.edu self.pic1.pio = bus.master 1136391Sksewell@umich.edu self.pic2.pio = bus.master 1146391Sksewell@umich.edu self.pit.pio = bus.master 1156642Sksewell@umich.edu self.speaker.pio = bus.master 1166391Sksewell@umich.edu self.io_apic.pio = bus.master 1176642Sksewell@umich.edu self.io_apic.int_master = bus.slave 1182833SN/A