xref: /gem5/src/dev/x86/SouthBridge.py

# Copyright (c) 2008 The Regents of The University of Michigan
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# Authors: Gabe Black

from m5.params import *
from m5.proxy import *
from Cmos import Cmos
from I82094AA import I82094AA
from I8237 import I8237
from I8254 import I8254
from I8259 import I8259
from PcSpeaker import PcSpeaker
from m5.SimObject import SimObject

def x86IOAddress(port):
    IO_address_space_base = 0x8000000000000000
    return IO_address_space_base + port;

class SouthBridge(SimObject):
    type = 'SouthBridge'
    pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
    platform = Param.Platform(Parent.any, "Platform this device is part of")

    _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master')
    _pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave')
    _cmos = Cmos(pio_addr=x86IOAddress(0x70))
    _dma1 = I8237(pio_addr=x86IOAddress(0x0))
    _pit = I8254(pio_addr=x86IOAddress(0x40))
    _speaker = PcSpeaker(pio_addr=x86IOAddress(0x61))
    _io_apic = I82094AA(pio_addr=0xFEC00000)

    pic1 = Param.I8259(_pic1, "Master PIC")
    pic2 = Param.I8259(_pic2, "Slave PIC")
    cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device")
    dma1 = Param.I8237(_dma1, "The first dma controller")
    pit = Param.I8254(_pit, "Programmable interval timer")
    speaker = Param.PcSpeaker(_speaker, "PC speaker")
    io_apic = Param.I82094AA(_io_apic, "I/O APIC")

    def attachIO(self, bus):
        # Make internal connections
        self.pic1.output = self.io_apic.pin(0)
        self.pic2.output = self.pic1.pin(2)
        self.cmos.int_pin = self.pic2.pin(0)
        self.pit.int_pin = self.pic1.pin(0)
        self.speaker.i8254 = self.pit
        # Connect to the bus
        self.cmos.pio = bus.port
        self.dma1.pio = bus.port
        self.pic1.pio = bus.port
        self.pic2.pio = bus.port
        self.pit.pio = bus.port
        self.speaker.pio = bus.port
        self.io_apic.pio = bus.port
        self.io_apic.int_port = bus.port