SouthBridge.py revision 5643
15390SN/A# Copyright (c) 2008 The Regents of The University of Michigan 25390SN/A# All rights reserved. 35390SN/A# 45390SN/A# Redistribution and use in source and binary forms, with or without 55390SN/A# modification, are permitted provided that the following conditions are 65390SN/A# met: redistributions of source code must retain the above copyright 75390SN/A# notice, this list of conditions and the following disclaimer; 85390SN/A# redistributions in binary form must reproduce the above copyright 95390SN/A# notice, this list of conditions and the following disclaimer in the 105390SN/A# documentation and/or other materials provided with the distribution; 115390SN/A# neither the name of the copyright holders nor the names of its 125390SN/A# contributors may be used to endorse or promote products derived from 135390SN/A# this software without specific prior written permission. 145390SN/A# 155390SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165390SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175390SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185390SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195390SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205390SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215390SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225390SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235390SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245390SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255390SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265390SN/A# 275390SN/A# Authors: Gabe Black 285390SN/A 295390SN/Afrom m5.params import * 305390SN/Afrom m5.proxy import * 315636SN/Afrom Cmos import Cmos 325643Sgblack@eecs.umich.edufrom I82094AA import I82094AA 335636SN/Afrom I8254 import I8254 345636SN/Afrom I8259 import I8259 355636SN/Afrom PcSpeaker import PcSpeaker 365636SN/Afrom m5.SimObject import SimObject 375390SN/A 385636SN/Adef x86IOAddress(port): 395636SN/A IO_address_space_base = 0x8000000000000000 405636SN/A return IO_address_space_base + port; 415636SN/A 425636SN/Aclass SouthBridge(SimObject): 435390SN/A type = 'SouthBridge' 445390SN/A pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") 455636SN/A platform = Param.Platform(Parent.any, "Platform this device is part of") 465636SN/A 475636SN/A _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master') 485636SN/A _pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave') 495636SN/A _cmos = Cmos(pio_addr=x86IOAddress(0x70)) 505636SN/A _pit = I8254(pio_addr=x86IOAddress(0x40)) 515636SN/A _speaker = PcSpeaker(pio_addr=x86IOAddress(0x61)) 525643Sgblack@eecs.umich.edu _io_apic = I82094AA(pio_addr=0xFEC00000) 535636SN/A 545636SN/A pic1 = Param.I8259(_pic1, "Master PIC") 555636SN/A pic2 = Param.I8259(_pic2, "Slave PIC") 565636SN/A cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device") 575636SN/A pit = Param.I8254(_pit, "Programmable interval timer") 585636SN/A speaker = Param.PcSpeaker(_speaker, "PC speaker") 595643Sgblack@eecs.umich.edu io_apic = Param.I82094AA(_io_apic, "I/O APIC") 605636SN/A 615636SN/A def attachIO(self, bus): 625636SN/A # Make internal connections 635643Sgblack@eecs.umich.edu self.pic1.output = self.io_apic.pin(0) 645636SN/A self.pic2.output = self.pic1.pin(2) 655636SN/A self.cmos.int_pin = self.pic2.pin(0) 665636SN/A self.pit.int_pin = self.pic1.pin(0) 675636SN/A self.speaker.i8254 = self.pit 685636SN/A # Connect to the bus 695636SN/A self.cmos.pio = bus.port 705636SN/A self.pic1.pio = bus.port 715636SN/A self.pic2.pio = bus.port 725636SN/A self.pit.pio = bus.port 735636SN/A self.speaker.pio = bus.port 745643Sgblack@eecs.umich.edu self.io_apic.pio = bus.port 75