ide_disk.cc revision 9956 
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andrew Schultz
41 *          Ali Saidi
42 */
43
44/** @file
45 * Device model implementation for an IDE disk
46 */
47
48#include <cerrno>
49#include <cstring>
50#include <deque>
51#include <string>
52
53#include "arch/isa_traits.hh"
54#include "base/chunk_generator.hh"
55#include "base/cprintf.hh" // csprintf
56#include "base/trace.hh"
57#include "config/the_isa.hh"
58#include "debug/IdeDisk.hh"
59#include "dev/disk_image.hh"
60#include "dev/ide_ctrl.hh"
61#include "dev/ide_disk.hh"
62#include "sim/core.hh"
63#include "sim/sim_object.hh"
64
65using namespace std;
66using namespace TheISA;
67
68IdeDisk::IdeDisk(const Params *p)
69    : SimObject(p), ctrl(NULL), image(p->image), diskDelay(p->delay),
70      dmaTransferEvent(this), dmaReadCG(NULL), dmaReadWaitEvent(this),
71      dmaWriteCG(NULL), dmaWriteWaitEvent(this), dmaPrdReadEvent(this),
72      dmaReadEvent(this), dmaWriteEvent(this)
73{
74    // Reset the device state
75    reset(p->driveID);
76
77    // fill out the drive ID structure
78    memset(&driveID, 0, sizeof(struct ataparams));
79
80    // Calculate LBA and C/H/S values
81    uint16_t cylinders;
82    uint8_t heads;
83    uint8_t sectors;
84
85    uint32_t lba_size = image->size();
86    if (lba_size >= 16383*16*63) {
87        cylinders = 16383;
88        heads = 16;
89        sectors = 63;
90    } else {
91        if (lba_size >= 63)
92            sectors = 63;
93        else
94            sectors = lba_size;
95
96        if ((lba_size / sectors) >= 16)
97            heads = 16;
98        else
99            heads = (lba_size / sectors);
100
101        cylinders = lba_size / (heads * sectors);
102    }
103
104    // Setup the model name
105    strncpy((char *)driveID.atap_model, "5MI EDD si k",
106            sizeof(driveID.atap_model));
107    // Set the maximum multisector transfer size
108    driveID.atap_multi = MAX_MULTSECT;
109    // IORDY supported, IORDY disabled, LBA enabled, DMA enabled
110    driveID.atap_capabilities1 = 0x7;
111    // UDMA support, EIDE support
112    driveID.atap_extensions = 0x6;
113    // Setup default C/H/S settings
114    driveID.atap_cylinders = cylinders;
115    driveID.atap_sectors = sectors;
116    driveID.atap_heads = heads;
117    // Setup the current multisector transfer size
118    driveID.atap_curmulti = MAX_MULTSECT;
119    driveID.atap_curmulti_valid = 0x1;
120    // Number of sectors on disk
121    driveID.atap_capacity = lba_size;
122    // Multiword DMA mode 2 and below supported
123    driveID.atap_dmamode_supp = 0x4;
124    // Set PIO mode 4 and 3 supported
125    driveID.atap_piomode_supp = 0x3;
126    // Set DMA mode 4 and below supported
127    driveID.atap_udmamode_supp = 0x1f;
128    // Statically set hardware config word
129    driveID.atap_hwreset_res = 0x4001;
130
131    //arbitrary for now...
132    driveID.atap_ata_major = WDC_VER_ATA7;
133}
134
135IdeDisk::~IdeDisk()
136{
137    // destroy the data buffer
138    delete [] dataBuffer;
139}
140
141void
142IdeDisk::reset(int id)
143{
144    // initialize the data buffer and shadow registers
145    dataBuffer = new uint8_t[MAX_DMA_SIZE];
146
147    memset(dataBuffer, 0, MAX_DMA_SIZE);
148    memset(&cmdReg, 0, sizeof(CommandReg_t));
149    memset(&curPrd.entry, 0, sizeof(PrdEntry_t));
150
151    curPrdAddr = 0;
152    curSector = 0;
153    cmdBytes = 0;
154    cmdBytesLeft = 0;
155    drqBytesLeft = 0;
156    dmaRead = false;
157    intrPending = false;
158    dmaAborted = false;
159
160    // set the device state to idle
161    dmaState = Dma_Idle;
162
163    if (id == DEV0) {
164        devState = Device_Idle_S;
165        devID = DEV0;
166    } else if (id == DEV1) {
167        devState = Device_Idle_NS;
168        devID = DEV1;
169    } else {
170        panic("Invalid device ID: %#x\n", id);
171    }
172
173    // set the device ready bit
174    status = STATUS_DRDY_BIT;
175
176    /* The error register must be set to 0x1 on start-up to
177       indicate that no diagnostic error was detected */
178    cmdReg.error = 0x1;
179}
180
181////
182// Utility functions
183////
184
185bool
186IdeDisk::isDEVSelect()
187{
188    return ctrl->isDiskSelected(this);
189}
190
191Addr
192IdeDisk::pciToDma(Addr pciAddr)
193{
194    if (ctrl)
195        return ctrl->pciToDma(pciAddr);
196    else
197        panic("Access to unset controller!\n");
198}
199
200////
201// Device registers read/write
202////
203
204void
205IdeDisk::readCommand(const Addr offset, int size, uint8_t *data)
206{
207    if (offset == DATA_OFFSET) {
208        if (size == sizeof(uint16_t)) {
209            *(uint16_t *)data = cmdReg.data;
210        } else if (size == sizeof(uint32_t)) {
211            *(uint16_t *)data = cmdReg.data;
212            updateState(ACT_DATA_READ_SHORT);
213            *((uint16_t *)data + 1) = cmdReg.data;
214        } else {
215            panic("Data read of unsupported size %d.\n", size);
216        }
217        updateState(ACT_DATA_READ_SHORT);
218        return;
219    }
220    assert(size == sizeof(uint8_t));
221    switch (offset) {
222      case ERROR_OFFSET:
223        *data = cmdReg.error;
224        break;
225      case NSECTOR_OFFSET:
226        *data = cmdReg.sec_count;
227        break;
228      case SECTOR_OFFSET:
229        *data = cmdReg.sec_num;
230        break;
231      case LCYL_OFFSET:
232        *data = cmdReg.cyl_low;
233        break;
234      case HCYL_OFFSET:
235        *data = cmdReg.cyl_high;
236        break;
237      case DRIVE_OFFSET:
238        *data = cmdReg.drive;
239        break;
240      case STATUS_OFFSET:
241        *data = status;
242        updateState(ACT_STAT_READ);
243        break;
244      default:
245        panic("Invalid IDE command register offset: %#x\n", offset);
246    }
247    DPRINTF(IdeDisk, "Read to disk at offset: %#x data %#x\n", offset, *data);
248}
249
250void
251IdeDisk::readControl(const Addr offset, int size, uint8_t *data)
252{
253    assert(size == sizeof(uint8_t));
254    *data = status;
255    if (offset != ALTSTAT_OFFSET)
256        panic("Invalid IDE control register offset: %#x\n", offset);
257    DPRINTF(IdeDisk, "Read to disk at offset: %#x data %#x\n", offset, *data);
258}
259
260void
261IdeDisk::writeCommand(const Addr offset, int size, const uint8_t *data)
262{
263    if (offset == DATA_OFFSET) {
264        if (size == sizeof(uint16_t)) {
265            cmdReg.data = *(const uint16_t *)data;
266        } else if (size == sizeof(uint32_t)) {
267            cmdReg.data = *(const uint16_t *)data;
268            updateState(ACT_DATA_WRITE_SHORT);
269            cmdReg.data = *((const uint16_t *)data + 1);
270        } else {
271            panic("Data write of unsupported size %d.\n", size);
272        }
273        updateState(ACT_DATA_WRITE_SHORT);
274        return;
275    }
276
277    assert(size == sizeof(uint8_t));
278    switch (offset) {
279      case FEATURES_OFFSET:
280        break;
281      case NSECTOR_OFFSET:
282        cmdReg.sec_count = *data;
283        break;
284      case SECTOR_OFFSET:
285        cmdReg.sec_num = *data;
286        break;
287      case LCYL_OFFSET:
288        cmdReg.cyl_low = *data;
289        break;
290      case HCYL_OFFSET:
291        cmdReg.cyl_high = *data;
292        break;
293      case DRIVE_OFFSET:
294        cmdReg.drive = *data;
295        updateState(ACT_SELECT_WRITE);
296        break;
297      case COMMAND_OFFSET:
298        cmdReg.command = *data;
299        updateState(ACT_CMD_WRITE);
300        break;
301      default:
302        panic("Invalid IDE command register offset: %#x\n", offset);
303    }
304    DPRINTF(IdeDisk, "Write to disk at offset: %#x data %#x\n", offset,
305            (uint32_t)*data);
306}
307
308void
309IdeDisk::writeControl(const Addr offset, int size, const uint8_t *data)
310{
311    if (offset != CONTROL_OFFSET)
312        panic("Invalid IDE control register offset: %#x\n", offset);
313
314    if (*data & CONTROL_RST_BIT) {
315        // force the device into the reset state
316        devState = Device_Srst;
317        updateState(ACT_SRST_SET);
318    } else if (devState == Device_Srst && !(*data & CONTROL_RST_BIT)) {
319        updateState(ACT_SRST_CLEAR);
320    }
321
322    nIENBit = *data & CONTROL_IEN_BIT;
323
324    DPRINTF(IdeDisk, "Write to disk at offset: %#x data %#x\n", offset,
325            (uint32_t)*data);
326}
327
328////
329// Perform DMA transactions
330////
331
332void
333IdeDisk::doDmaTransfer()
334{
335    if (dmaAborted) {
336        DPRINTF(IdeDisk, "DMA Aborted before reading PRD entry\n");
337        updateState(ACT_CMD_ERROR);
338        return;
339    }
340
341    if (dmaState != Dma_Transfer || devState != Transfer_Data_Dma)
342        panic("Inconsistent DMA transfer state: dmaState = %d devState = %d\n",
343              dmaState, devState);
344
345    if (ctrl->dmaPending() || ctrl->getDrainState() != Drainable::Running) {
346        schedule(dmaTransferEvent, curTick() + DMA_BACKOFF_PERIOD);
347        return;
348    } else
349        ctrl->dmaRead(curPrdAddr, sizeof(PrdEntry_t), &dmaPrdReadEvent,
350                (uint8_t*)&curPrd.entry);
351}
352
353void
354IdeDisk::dmaPrdReadDone()
355{
356    if (dmaAborted) {
357        DPRINTF(IdeDisk, "DMA Aborted while reading PRD entry\n");
358        updateState(ACT_CMD_ERROR);
359        return;
360    }
361
362    DPRINTF(IdeDisk,
363            "PRD: baseAddr:%#x (%#x) byteCount:%d (%d) eot:%#x sector:%d\n",
364            curPrd.getBaseAddr(), pciToDma(curPrd.getBaseAddr()),
365            curPrd.getByteCount(), (cmdBytesLeft/SectorSize),
366            curPrd.getEOT(), curSector);
367
368    // the prd pointer has already been translated, so just do an increment
369    curPrdAddr = curPrdAddr + sizeof(PrdEntry_t);
370
371    if (dmaRead)
372        doDmaDataRead();
373    else
374        doDmaDataWrite();
375}
376
377void
378IdeDisk::doDmaDataRead()
379{
380    /** @todo we need to figure out what the delay actually will be */
381    Tick totalDiskDelay = diskDelay + (curPrd.getByteCount() / SectorSize);
382
383    DPRINTF(IdeDisk, "doDmaRead, diskDelay: %d totalDiskDelay: %d\n",
384            diskDelay, totalDiskDelay);
385
386    schedule(dmaReadWaitEvent, curTick() + totalDiskDelay);
387}
388
389void
390IdeDisk::regStats()
391{
392    using namespace Stats;
393    dmaReadFullPages
394        .name(name() + ".dma_read_full_pages")
395        .desc("Number of full page size DMA reads (not PRD).")
396        ;
397    dmaReadBytes
398        .name(name() + ".dma_read_bytes")
399        .desc("Number of bytes transfered via DMA reads (not PRD).")
400        ;
401    dmaReadTxs
402        .name(name() + ".dma_read_txs")
403        .desc("Number of DMA read transactions (not PRD).")
404        ;
405
406    dmaWriteFullPages
407        .name(name() + ".dma_write_full_pages")
408        .desc("Number of full page size DMA writes.")
409        ;
410    dmaWriteBytes
411        .name(name() + ".dma_write_bytes")
412        .desc("Number of bytes transfered via DMA writes.")
413        ;
414    dmaWriteTxs
415        .name(name() + ".dma_write_txs")
416        .desc("Number of DMA write transactions.")
417        ;
418}
419
420void
421IdeDisk::doDmaRead()
422{
423    if (dmaAborted) {
424        DPRINTF(IdeDisk, "DMA Aborted in middle of Dma Read\n");
425        if (dmaReadCG)
426            delete dmaReadCG;
427        dmaReadCG = NULL;
428        updateState(ACT_CMD_ERROR);
429        return;
430    }
431
432    if (!dmaReadCG) {
433        // clear out the data buffer
434        memset(dataBuffer, 0, MAX_DMA_SIZE);
435        dmaReadCG = new ChunkGenerator(curPrd.getBaseAddr(),
436                curPrd.getByteCount(), TheISA::PageBytes);
437
438    }
439    if (ctrl->dmaPending() || ctrl->getDrainState() != Drainable::Running) {
440        schedule(dmaReadWaitEvent, curTick() + DMA_BACKOFF_PERIOD);
441        return;
442    } else if (!dmaReadCG->done()) {
443        assert(dmaReadCG->complete() < MAX_DMA_SIZE);
444        ctrl->dmaRead(pciToDma(dmaReadCG->addr()), dmaReadCG->size(),
445                &dmaReadWaitEvent, dataBuffer + dmaReadCG->complete());
446        dmaReadBytes += dmaReadCG->size();
447        dmaReadTxs++;
448        if (dmaReadCG->size() == TheISA::PageBytes)
449            dmaReadFullPages++;
450        dmaReadCG->next();
451    } else {
452        assert(dmaReadCG->done());
453        delete dmaReadCG;
454        dmaReadCG = NULL;
455        dmaReadDone();
456    }
457}
458
459void
460IdeDisk::dmaReadDone()
461{
462    uint32_t bytesWritten = 0;
463
464    // write the data to the disk image
465    for (bytesWritten = 0; bytesWritten < curPrd.getByteCount();
466         bytesWritten += SectorSize) {
467
468        cmdBytesLeft -= SectorSize;
469        writeDisk(curSector++, (uint8_t *)(dataBuffer + bytesWritten));
470    }
471
472    // check for the EOT
473    if (curPrd.getEOT()) {
474        assert(cmdBytesLeft == 0);
475        dmaState = Dma_Idle;
476        updateState(ACT_DMA_DONE);
477    } else {
478        doDmaTransfer();
479    }
480}
481
482void
483IdeDisk::doDmaDataWrite()
484{
485    /** @todo we need to figure out what the delay actually will be */
486    Tick totalDiskDelay = diskDelay + (curPrd.getByteCount() / SectorSize);
487    uint32_t bytesRead = 0;
488
489    DPRINTF(IdeDisk, "doDmaWrite, diskDelay: %d totalDiskDelay: %d\n",
490            diskDelay, totalDiskDelay);
491
492    memset(dataBuffer, 0, MAX_DMA_SIZE);
493    assert(cmdBytesLeft <= MAX_DMA_SIZE);
494    while (bytesRead < curPrd.getByteCount()) {
495        readDisk(curSector++, (uint8_t *)(dataBuffer + bytesRead));
496        bytesRead += SectorSize;
497        cmdBytesLeft -= SectorSize;
498    }
499    DPRINTF(IdeDisk, "doDmaWrite, bytesRead: %d cmdBytesLeft: %d\n",
500            bytesRead, cmdBytesLeft);
501
502    schedule(dmaWriteWaitEvent, curTick() + totalDiskDelay);
503}
504
505void
506IdeDisk::doDmaWrite()
507{
508    if (dmaAborted) {
509        DPRINTF(IdeDisk, "DMA Aborted while doing DMA Write\n");
510        if (dmaWriteCG)
511            delete dmaWriteCG;
512        dmaWriteCG = NULL;
513        updateState(ACT_CMD_ERROR);
514        return;
515    }
516    if (!dmaWriteCG) {
517        // clear out the data buffer
518        dmaWriteCG = new ChunkGenerator(curPrd.getBaseAddr(),
519                curPrd.getByteCount(), TheISA::PageBytes);
520    }
521    if (ctrl->dmaPending() || ctrl->getDrainState() != Drainable::Running) {
522        schedule(dmaWriteWaitEvent, curTick() + DMA_BACKOFF_PERIOD);
523        DPRINTF(IdeDisk, "doDmaWrite: rescheduling\n");
524        return;
525    } else if (!dmaWriteCG->done()) {
526        assert(dmaWriteCG->complete() < MAX_DMA_SIZE);
527        ctrl->dmaWrite(pciToDma(dmaWriteCG->addr()), dmaWriteCG->size(),
528                &dmaWriteWaitEvent, dataBuffer + dmaWriteCG->complete());
529        DPRINTF(IdeDisk, "doDmaWrite: not done curPrd byte count %d, eot %#x\n",
530                curPrd.getByteCount(), curPrd.getEOT());
531        dmaWriteBytes += dmaWriteCG->size();
532        dmaWriteTxs++;
533        if (dmaWriteCG->size() == TheISA::PageBytes)
534            dmaWriteFullPages++;
535        dmaWriteCG->next();
536    } else {
537        DPRINTF(IdeDisk, "doDmaWrite: done curPrd byte count %d, eot %#x\n",
538                curPrd.getByteCount(), curPrd.getEOT());
539        assert(dmaWriteCG->done());
540        delete dmaWriteCG;
541        dmaWriteCG = NULL;
542        dmaWriteDone();
543    }
544}
545
546void
547IdeDisk::dmaWriteDone()
548{
549    DPRINTF(IdeDisk, "doWriteDone: curPrd byte count %d, eot %#x cmd bytes left:%d\n",
550                curPrd.getByteCount(), curPrd.getEOT(), cmdBytesLeft);
551    // check for the EOT
552    if (curPrd.getEOT()) {
553        assert(cmdBytesLeft == 0);
554        dmaState = Dma_Idle;
555        updateState(ACT_DMA_DONE);
556    } else {
557        doDmaTransfer();
558    }
559}
560
561////
562// Disk utility routines
563///
564
565void
566IdeDisk::readDisk(uint32_t sector, uint8_t *data)
567{
568    uint32_t bytesRead = image->read(data, sector);
569
570    if (bytesRead != SectorSize)
571        panic("Can't read from %s. Only %d of %d read. errno=%d\n",
572              name(), bytesRead, SectorSize, errno);
573}
574
575void
576IdeDisk::writeDisk(uint32_t sector, uint8_t *data)
577{
578    uint32_t bytesWritten = image->write(data, sector);
579
580    if (bytesWritten != SectorSize)
581        panic("Can't write to %s. Only %d of %d written. errno=%d\n",
582              name(), bytesWritten, SectorSize, errno);
583}
584
585////
586// Setup and handle commands
587////
588
589void
590IdeDisk::startDma(const uint32_t &prdTableBase)
591{
592    if (dmaState != Dma_Start)
593        panic("Inconsistent DMA state, should be in Dma_Start!\n");
594
595    if (devState != Transfer_Data_Dma)
596        panic("Inconsistent device state for DMA start!\n");
597
598    // PRD base address is given by bits 31:2
599    curPrdAddr = pciToDma((Addr)(prdTableBase & ~ULL(0x3)));
600
601    dmaState = Dma_Transfer;
602
603    // schedule dma transfer (doDmaTransfer)
604    schedule(dmaTransferEvent, curTick() + 1);
605}
606
607void
608IdeDisk::abortDma()
609{
610    if (dmaState == Dma_Idle)
611        panic("Inconsistent DMA state, should be Start or Transfer!");
612
613    if (devState != Transfer_Data_Dma && devState != Prepare_Data_Dma)
614        panic("Inconsistent device state, should be Transfer or Prepare!\n");
615
616    updateState(ACT_CMD_ERROR);
617}
618
619void
620IdeDisk::startCommand()
621{
622    DevAction_t action = ACT_NONE;
623    uint32_t size = 0;
624    dmaRead = false;
625
626    // Decode commands
627    switch (cmdReg.command) {
628        // Supported non-data commands
629      case WDSF_READ_NATIVE_MAX:
630        size = (uint32_t)image->size() - 1;
631        cmdReg.sec_num = (size & 0xff);
632        cmdReg.cyl_low = ((size & 0xff00) >> 8);
633        cmdReg.cyl_high = ((size & 0xff0000) >> 16);
634        cmdReg.head = ((size & 0xf000000) >> 24);
635
636        devState = Command_Execution;
637        action = ACT_CMD_COMPLETE;
638        break;
639
640      case WDCC_RECAL:
641      case WDCC_IDP:
642      case WDCC_STANDBY_IMMED:
643      case WDCC_FLUSHCACHE:
644      case WDSF_VERIFY:
645      case WDSF_SEEK:
646      case SET_FEATURES:
647      case WDCC_SETMULTI:
648        devState = Command_Execution;
649        action = ACT_CMD_COMPLETE;
650        break;
651
652        // Supported PIO data-in commands
653      case WDCC_IDENTIFY:
654        cmdBytes = cmdBytesLeft = sizeof(struct ataparams);
655        devState = Prepare_Data_In;
656        action = ACT_DATA_READY;
657        break;
658
659      case WDCC_READMULTI:
660      case WDCC_READ:
661        if (!(cmdReg.drive & DRIVE_LBA_BIT))
662            panic("Attempt to perform CHS access, only supports LBA\n");
663
664        if (cmdReg.sec_count == 0)
665            cmdBytes = cmdBytesLeft = (256 * SectorSize);
666        else
667            cmdBytes = cmdBytesLeft = (cmdReg.sec_count * SectorSize);
668
669        curSector = getLBABase();
670
671        /** @todo make this a scheduled event to simulate disk delay */
672        devState = Prepare_Data_In;
673        action = ACT_DATA_READY;
674        break;
675
676        // Supported PIO data-out commands
677      case WDCC_WRITEMULTI:
678      case WDCC_WRITE:
679        if (!(cmdReg.drive & DRIVE_LBA_BIT))
680            panic("Attempt to perform CHS access, only supports LBA\n");
681
682        if (cmdReg.sec_count == 0)
683            cmdBytes = cmdBytesLeft = (256 * SectorSize);
684        else
685            cmdBytes = cmdBytesLeft = (cmdReg.sec_count * SectorSize);
686        DPRINTF(IdeDisk, "Setting cmdBytesLeft to %d\n", cmdBytesLeft);
687        curSector = getLBABase();
688
689        devState = Prepare_Data_Out;
690        action = ACT_DATA_READY;
691        break;
692
693        // Supported DMA commands
694      case WDCC_WRITEDMA:
695        dmaRead = true;  // a write to the disk is a DMA read from memory
696      case WDCC_READDMA:
697        if (!(cmdReg.drive & DRIVE_LBA_BIT))
698            panic("Attempt to perform CHS access, only supports LBA\n");
699
700        if (cmdReg.sec_count == 0)
701            cmdBytes = cmdBytesLeft = (256 * SectorSize);
702        else
703            cmdBytes = cmdBytesLeft = (cmdReg.sec_count * SectorSize);
704        DPRINTF(IdeDisk, "Setting cmdBytesLeft to %d in readdma\n", cmdBytesLeft);
705
706        curSector = getLBABase();
707
708        devState = Prepare_Data_Dma;
709        action = ACT_DMA_READY;
710        break;
711
712      default:
713        panic("Unsupported ATA command: %#x\n", cmdReg.command);
714    }
715
716    if (action != ACT_NONE) {
717        // set the BSY bit
718        status |= STATUS_BSY_BIT;
719        // clear the DRQ bit
720        status &= ~STATUS_DRQ_BIT;
721        // clear the DF bit
722        status &= ~STATUS_DF_BIT;
723
724        updateState(action);
725    }
726}
727
728////
729// Handle setting and clearing interrupts
730////
731
732void
733IdeDisk::intrPost()
734{
735    DPRINTF(IdeDisk, "Posting Interrupt\n");
736    if (intrPending)
737        panic("Attempt to post an interrupt with one pending\n");
738
739    intrPending = true;
740
741    // talk to controller to set interrupt
742    if (ctrl) {
743        ctrl->intrPost();
744    }
745}
746
747void
748IdeDisk::intrClear()
749{
750    DPRINTF(IdeDisk, "Clearing Interrupt\n");
751    if (!intrPending)
752        panic("Attempt to clear a non-pending interrupt\n");
753
754    intrPending = false;
755
756    // talk to controller to clear interrupt
757    if (ctrl)
758        ctrl->intrClear();
759}
760
761////
762// Manage the device internal state machine
763////
764
765void
766IdeDisk::updateState(DevAction_t action)
767{
768    switch (devState) {
769      case Device_Srst:
770        if (action == ACT_SRST_SET) {
771            // set the BSY bit
772            status |= STATUS_BSY_BIT;
773        } else if (action == ACT_SRST_CLEAR) {
774            // clear the BSY bit
775            status &= ~STATUS_BSY_BIT;
776
777            // reset the device state
778            reset(devID);
779        }
780        break;
781
782      case Device_Idle_S:
783        if (action == ACT_SELECT_WRITE && !isDEVSelect()) {
784            devState = Device_Idle_NS;
785        } else if (action == ACT_CMD_WRITE) {
786            startCommand();
787        }
788
789        break;
790
791      case Device_Idle_SI:
792        if (action == ACT_SELECT_WRITE && !isDEVSelect()) {
793            devState = Device_Idle_NS;
794            intrClear();
795        } else if (action == ACT_STAT_READ || isIENSet()) {
796            devState = Device_Idle_S;
797            intrClear();
798        } else if (action == ACT_CMD_WRITE) {
799            intrClear();
800            startCommand();
801        }
802
803        break;
804
805      case Device_Idle_NS:
806        if (action == ACT_SELECT_WRITE && isDEVSelect()) {
807            if (!isIENSet() && intrPending) {
808                devState = Device_Idle_SI;
809                intrPost();
810            }
811            if (isIENSet() || !intrPending) {
812                devState = Device_Idle_S;
813            }
814        }
815        break;
816
817      case Command_Execution:
818        if (action == ACT_CMD_COMPLETE) {
819            // clear the BSY bit
820            setComplete();
821
822            if (!isIENSet()) {
823                devState = Device_Idle_SI;
824                intrPost();
825            } else {
826                devState = Device_Idle_S;
827            }
828        }
829        break;
830
831      case Prepare_Data_In:
832        if (action == ACT_CMD_ERROR) {
833            // clear the BSY bit
834            setComplete();
835
836            if (!isIENSet()) {
837                devState = Device_Idle_SI;
838                intrPost();
839            } else {
840                devState = Device_Idle_S;
841            }
842        } else if (action == ACT_DATA_READY) {
843            // clear the BSY bit
844            status &= ~STATUS_BSY_BIT;
845            // set the DRQ bit
846            status |= STATUS_DRQ_BIT;
847
848            // copy the data into the data buffer
849            if (cmdReg.command == WDCC_IDENTIFY) {
850                // Reset the drqBytes for this block
851                drqBytesLeft = sizeof(struct ataparams);
852
853                memcpy((void *)dataBuffer, (void *)&driveID,
854                       sizeof(struct ataparams));
855            } else {
856                // Reset the drqBytes for this block
857                drqBytesLeft = SectorSize;
858
859                readDisk(curSector++, dataBuffer);
860            }
861
862            // put the first two bytes into the data register
863            memcpy((void *)&cmdReg.data, (void *)dataBuffer,
864                   sizeof(uint16_t));
865
866            if (!isIENSet()) {
867                devState = Data_Ready_INTRQ_In;
868                intrPost();
869            } else {
870                devState = Transfer_Data_In;
871            }
872        }
873        break;
874
875      case Data_Ready_INTRQ_In:
876        if (action == ACT_STAT_READ) {
877            devState = Transfer_Data_In;
878            intrClear();
879        }
880        break;
881
882      case Transfer_Data_In:
883        if (action == ACT_DATA_READ_BYTE || action == ACT_DATA_READ_SHORT) {
884            if (action == ACT_DATA_READ_BYTE) {
885                panic("DEBUG: READING DATA ONE BYTE AT A TIME!\n");
886            } else {
887                drqBytesLeft -= 2;
888                cmdBytesLeft -= 2;
889
890                // copy next short into data registers
891                if (drqBytesLeft)
892                    memcpy((void *)&cmdReg.data,
893                           (void *)&dataBuffer[SectorSize - drqBytesLeft],
894                           sizeof(uint16_t));
895            }
896
897            if (drqBytesLeft == 0) {
898                if (cmdBytesLeft == 0) {
899                    // Clear the BSY bit
900                    setComplete();
901                    devState = Device_Idle_S;
902                } else {
903                    devState = Prepare_Data_In;
904                    // set the BSY_BIT
905                    status |= STATUS_BSY_BIT;
906                    // clear the DRQ_BIT
907                    status &= ~STATUS_DRQ_BIT;
908
909                    /** @todo change this to a scheduled event to simulate
910                        disk delay */
911                    updateState(ACT_DATA_READY);
912                }
913            }
914        }
915        break;
916
917      case Prepare_Data_Out:
918        if (action == ACT_CMD_ERROR || cmdBytesLeft == 0) {
919            // clear the BSY bit
920            setComplete();
921
922            if (!isIENSet()) {
923                devState = Device_Idle_SI;
924                intrPost();
925            } else {
926                devState = Device_Idle_S;
927            }
928        } else if (action == ACT_DATA_READY && cmdBytesLeft != 0) {
929            // clear the BSY bit
930            status &= ~STATUS_BSY_BIT;
931            // set the DRQ bit
932            status |= STATUS_DRQ_BIT;
933
934            // clear the data buffer to get it ready for writes
935            memset(dataBuffer, 0, MAX_DMA_SIZE);
936
937            // reset the drqBytes for this block
938            drqBytesLeft = SectorSize;
939
940            if (cmdBytesLeft == cmdBytes || isIENSet()) {
941                devState = Transfer_Data_Out;
942            } else {
943                devState = Data_Ready_INTRQ_Out;
944                intrPost();
945            }
946        }
947        break;
948
949      case Data_Ready_INTRQ_Out:
950        if (action == ACT_STAT_READ) {
951            devState = Transfer_Data_Out;
952            intrClear();
953        }
954        break;
955
956      case Transfer_Data_Out:
957        if (action == ACT_DATA_WRITE_BYTE ||
958            action == ACT_DATA_WRITE_SHORT) {
959
960            if (action == ACT_DATA_READ_BYTE) {
961                panic("DEBUG: WRITING DATA ONE BYTE AT A TIME!\n");
962            } else {
963                // copy the latest short into the data buffer
964                memcpy((void *)&dataBuffer[SectorSize - drqBytesLeft],
965                       (void *)&cmdReg.data,
966                       sizeof(uint16_t));
967
968                drqBytesLeft -= 2;
969                cmdBytesLeft -= 2;
970            }
971
972            if (drqBytesLeft == 0) {
973                // copy the block to the disk
974                writeDisk(curSector++, dataBuffer);
975
976                // set the BSY bit
977                status |= STATUS_BSY_BIT;
978                // set the seek bit
979                status |= STATUS_SEEK_BIT;
980                // clear the DRQ bit
981                status &= ~STATUS_DRQ_BIT;
982
983                devState = Prepare_Data_Out;
984
985                /** @todo change this to a scheduled event to simulate
986                    disk delay */
987                updateState(ACT_DATA_READY);
988            }
989        }
990        break;
991
992      case Prepare_Data_Dma:
993        if (action == ACT_CMD_ERROR) {
994            // clear the BSY bit
995            setComplete();
996
997            if (!isIENSet()) {
998                devState = Device_Idle_SI;
999                intrPost();
1000            } else {
1001                devState = Device_Idle_S;
1002            }
1003        } else if (action == ACT_DMA_READY) {
1004            // clear the BSY bit
1005            status &= ~STATUS_BSY_BIT;
1006            // set the DRQ bit
1007            status |= STATUS_DRQ_BIT;
1008
1009            devState = Transfer_Data_Dma;
1010
1011            if (dmaState != Dma_Idle)
1012                panic("Inconsistent DMA state, should be Dma_Idle\n");
1013
1014            dmaState = Dma_Start;
1015            // wait for the write to the DMA start bit
1016        }
1017        break;
1018
1019      case Transfer_Data_Dma:
1020        if (action == ACT_CMD_ERROR) {
1021            dmaAborted = true;
1022            devState = Device_Dma_Abort;
1023        } else if (action == ACT_DMA_DONE) {
1024            // clear the BSY bit
1025            setComplete();
1026            // set the seek bit
1027            status |= STATUS_SEEK_BIT;
1028            // clear the controller state for DMA transfer
1029            ctrl->setDmaComplete(this);
1030
1031            if (!isIENSet()) {
1032                devState = Device_Idle_SI;
1033                intrPost();
1034            } else {
1035                devState = Device_Idle_S;
1036            }
1037        }
1038        break;
1039
1040      case Device_Dma_Abort:
1041        if (action == ACT_CMD_ERROR) {
1042            setComplete();
1043            status |= STATUS_SEEK_BIT;
1044            ctrl->setDmaComplete(this);
1045            dmaAborted = false;
1046            dmaState = Dma_Idle;
1047
1048            if (!isIENSet()) {
1049                devState = Device_Idle_SI;
1050                intrPost();
1051            } else {
1052                devState = Device_Idle_S;
1053            }
1054        } else {
1055            DPRINTF(IdeDisk, "Disk still busy aborting previous DMA command\n");
1056        }
1057        break;
1058
1059      default:
1060        panic("Unknown IDE device state: %#x\n", devState);
1061    }
1062}
1063
1064void
1065IdeDisk::serialize(ostream &os)
1066{
1067    // Check all outstanding events to see if they are scheduled
1068    // these are all mutually exclusive
1069    Tick reschedule = 0;
1070    Events_t event = None;
1071
1072    int eventCount = 0;
1073
1074    if (dmaTransferEvent.scheduled()) {
1075        reschedule = dmaTransferEvent.when();
1076        event = Transfer;
1077        eventCount++;
1078    }
1079    if (dmaReadWaitEvent.scheduled()) {
1080        reschedule = dmaReadWaitEvent.when();
1081        event = ReadWait;
1082        eventCount++;
1083    }
1084    if (dmaWriteWaitEvent.scheduled()) {
1085        reschedule = dmaWriteWaitEvent.when();
1086        event = WriteWait;
1087        eventCount++;
1088    }
1089    if (dmaPrdReadEvent.scheduled()) {
1090        reschedule = dmaPrdReadEvent.when();
1091        event = PrdRead;
1092        eventCount++;
1093    }
1094    if (dmaReadEvent.scheduled()) {
1095        reschedule = dmaReadEvent.when();
1096        event = DmaRead;
1097        eventCount++;
1098    }
1099    if (dmaWriteEvent.scheduled()) {
1100        reschedule = dmaWriteEvent.when();
1101        event = DmaWrite;
1102        eventCount++;
1103    }
1104
1105    assert(eventCount <= 1);
1106
1107    SERIALIZE_SCALAR(reschedule);
1108    SERIALIZE_ENUM(event);
1109
1110    // Serialize device registers
1111    SERIALIZE_SCALAR(cmdReg.data);
1112    SERIALIZE_SCALAR(cmdReg.sec_count);
1113    SERIALIZE_SCALAR(cmdReg.sec_num);
1114    SERIALIZE_SCALAR(cmdReg.cyl_low);
1115    SERIALIZE_SCALAR(cmdReg.cyl_high);
1116    SERIALIZE_SCALAR(cmdReg.drive);
1117    SERIALIZE_SCALAR(cmdReg.command);
1118    SERIALIZE_SCALAR(status);
1119    SERIALIZE_SCALAR(nIENBit);
1120    SERIALIZE_SCALAR(devID);
1121
1122    // Serialize the PRD related information
1123    SERIALIZE_SCALAR(curPrd.entry.baseAddr);
1124    SERIALIZE_SCALAR(curPrd.entry.byteCount);
1125    SERIALIZE_SCALAR(curPrd.entry.endOfTable);
1126    SERIALIZE_SCALAR(curPrdAddr);
1127
1128    /** @todo need to serialized chunk generator stuff!! */
1129    // Serialize current transfer related information
1130    SERIALIZE_SCALAR(cmdBytesLeft);
1131    SERIALIZE_SCALAR(cmdBytes);
1132    SERIALIZE_SCALAR(drqBytesLeft);
1133    SERIALIZE_SCALAR(curSector);
1134    SERIALIZE_SCALAR(dmaRead);
1135    SERIALIZE_SCALAR(intrPending);
1136    SERIALIZE_SCALAR(dmaAborted);
1137    SERIALIZE_ENUM(devState);
1138    SERIALIZE_ENUM(dmaState);
1139    SERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
1140}
1141
1142void
1143IdeDisk::unserialize(Checkpoint *cp, const string &section)
1144{
1145    // Reschedule events that were outstanding
1146    // these are all mutually exclusive
1147    Tick reschedule = 0;
1148    Events_t event = None;
1149
1150    UNSERIALIZE_SCALAR(reschedule);
1151    UNSERIALIZE_ENUM(event);
1152
1153    switch (event) {
1154      case None : break;
1155      case Transfer : schedule(dmaTransferEvent, reschedule); break;
1156      case ReadWait : schedule(dmaReadWaitEvent, reschedule); break;
1157      case WriteWait : schedule(dmaWriteWaitEvent, reschedule); break;
1158      case PrdRead : schedule(dmaPrdReadEvent, reschedule); break;
1159      case DmaRead : schedule(dmaReadEvent, reschedule); break;
1160      case DmaWrite : schedule(dmaWriteEvent, reschedule); break;
1161    }
1162
1163    // Unserialize device registers
1164    UNSERIALIZE_SCALAR(cmdReg.data);
1165    UNSERIALIZE_SCALAR(cmdReg.sec_count);
1166    UNSERIALIZE_SCALAR(cmdReg.sec_num);
1167    UNSERIALIZE_SCALAR(cmdReg.cyl_low);
1168    UNSERIALIZE_SCALAR(cmdReg.cyl_high);
1169    UNSERIALIZE_SCALAR(cmdReg.drive);
1170    UNSERIALIZE_SCALAR(cmdReg.command);
1171    UNSERIALIZE_SCALAR(status);
1172    UNSERIALIZE_SCALAR(nIENBit);
1173    UNSERIALIZE_SCALAR(devID);
1174
1175    // Unserialize the PRD related information
1176    UNSERIALIZE_SCALAR(curPrd.entry.baseAddr);
1177    UNSERIALIZE_SCALAR(curPrd.entry.byteCount);
1178    UNSERIALIZE_SCALAR(curPrd.entry.endOfTable);
1179    UNSERIALIZE_SCALAR(curPrdAddr);
1180
1181    /** @todo need to serialized chunk generator stuff!! */
1182    // Unserialize current transfer related information
1183    UNSERIALIZE_SCALAR(cmdBytes);
1184    UNSERIALIZE_SCALAR(cmdBytesLeft);
1185    UNSERIALIZE_SCALAR(drqBytesLeft);
1186    UNSERIALIZE_SCALAR(curSector);
1187    UNSERIALIZE_SCALAR(dmaRead);
1188    UNSERIALIZE_SCALAR(intrPending);
1189    UNSERIALIZE_SCALAR(dmaAborted);
1190    UNSERIALIZE_ENUM(devState);
1191    UNSERIALIZE_ENUM(dmaState);
1192    UNSERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
1193}
1194
1195IdeDisk *
1196IdeDiskParams::create()
1197{
1198    return new IdeDisk(this);
1199}
1200