ide_ctrl.hh revision 848
110915Sandreas.sandberg@arm.com/* 210915Sandreas.sandberg@arm.com * Copyright (c) 2003 The Regents of The University of Michigan 310915Sandreas.sandberg@arm.com * All rights reserved. 410915Sandreas.sandberg@arm.com * 510915Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 610915Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 710915Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 810915Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 910915Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1010915Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1110915Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1210915Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1310915Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1410915Sandreas.sandberg@arm.com * this software without specific prior written permission. 1510915Sandreas.sandberg@arm.com * 1610915Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710915Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810915Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910915Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010915Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110915Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210915Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310915Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410915Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510915Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610915Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710915Sandreas.sandberg@arm.com */ 2810915Sandreas.sandberg@arm.com 2910915Sandreas.sandberg@arm.com/** @file 3010915Sandreas.sandberg@arm.com * Simple PCI IDE controller with bus mastering capability 3110915Sandreas.sandberg@arm.com */ 3210915Sandreas.sandberg@arm.com 3310915Sandreas.sandberg@arm.com#ifndef __IDE_CTRL_HH__ 3410915Sandreas.sandberg@arm.com#define __IDE_CTRL_HH__ 3510915Sandreas.sandberg@arm.com 3610915Sandreas.sandberg@arm.com#include "dev/pcidev.hh" 3710915Sandreas.sandberg@arm.com#include "dev/pcireg.h" 3810915Sandreas.sandberg@arm.com#include "dev/io_device.hh" 3910915Sandreas.sandberg@arm.com 4010915Sandreas.sandberg@arm.com#define CMD0 0x00 // Channel 0 command block offset 4110915Sandreas.sandberg@arm.com#define CTRL0 0x08 // Channel 0 control block offset 4210915Sandreas.sandberg@arm.com#define CMD1 0x0c // Channel 1 command block offset 4310915Sandreas.sandberg@arm.com#define CTRL1 0x14 // Channel 1 control block offset 4411313Sandreas.sandberg@arm.com#define BMI 0x18 // Bus master IDE offset 4511313Sandreas.sandberg@arm.com 4611313Sandreas.sandberg@arm.com#define BMIC0 0x0 // Bus master IDE command register 4711313Sandreas.sandberg@arm.com#define BMIS0 0x2 // Bus master IDE status register 4811313Sandreas.sandberg@arm.com#define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register 4911313Sandreas.sandberg@arm.com#define BMIC1 0x8 // Bus master IDE command register 5011313Sandreas.sandberg@arm.com#define BMIS1 0xa // Bus master IDE status register 5111313Sandreas.sandberg@arm.com#define BMIDTP1 0xc // Bus master IDE descriptor table pointer register 5211313Sandreas.sandberg@arm.com 5310915Sandreas.sandberg@arm.com// Bus master IDE command register bit fields 5410915Sandreas.sandberg@arm.com#define RWCON 0x08 // Bus master read/write control 5510915Sandreas.sandberg@arm.com#define SSBM 0x01 // Start/stop bus master 5610915Sandreas.sandberg@arm.com 5710915Sandreas.sandberg@arm.com// Bus master IDE status register bit fields 5810915Sandreas.sandberg@arm.com#define DMA1CAP 0x40 // Drive 1 DMA capable 5910915Sandreas.sandberg@arm.com#define DMA0CAP 0x20 // Drive 0 DMA capable 6010915Sandreas.sandberg@arm.com#define IDEINTS 0x04 // IDE Interrupt Status 6110915Sandreas.sandberg@arm.com#define IDEDMAE 0x02 // IDE DMA error 6210915Sandreas.sandberg@arm.com#define BMIDEA 0x01 // Bus master IDE active 6310915Sandreas.sandberg@arm.com 6410915Sandreas.sandberg@arm.com// IDE Command byte fields 6510915Sandreas.sandberg@arm.com// Taken from include/linux/ide.h 6610915Sandreas.sandberg@arm.com#define IDE_DATA_OFFSET (0) 6710915Sandreas.sandberg@arm.com#define IDE_ERROR_OFFSET (1) 6810915Sandreas.sandberg@arm.com#define IDE_NSECTOR_OFFSET (2) 6910915Sandreas.sandberg@arm.com#define IDE_SECTOR_OFFSET (3) 7010915Sandreas.sandberg@arm.com#define IDE_LCYL_OFFSET (4) 7110915Sandreas.sandberg@arm.com#define IDE_HCYL_OFFSET (5) 7210915Sandreas.sandberg@arm.com#define IDE_SELECT_OFFSET (6) 7310915Sandreas.sandberg@arm.com#define IDE_STATUS_OFFSET (7) 7410915Sandreas.sandberg@arm.com#define IDE_CONTROL_OFFSET (8) 7510915Sandreas.sandberg@arm.com#define IDE_IRQ_OFFSET (9) 7610915Sandreas.sandberg@arm.com 7710915Sandreas.sandberg@arm.com#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET 7810915Sandreas.sandberg@arm.com#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET 7910915Sandreas.sandberg@arm.com 8010915Sandreas.sandberg@arm.com// PCI device specific register byte offsets 8110915Sandreas.sandberg@arm.com#define PCI_IDE_TIMING 0x40 8210915Sandreas.sandberg@arm.com#define PCI_SLAVE_TIMING 0x44 8310915Sandreas.sandberg@arm.com#define PCI_UDMA33_CTRL 0x48 8410915Sandreas.sandberg@arm.com#define PCI_UDMA33_TIMING 0x4a 8510915Sandreas.sandberg@arm.com 8610915Sandreas.sandberg@arm.com#define IDETIM (0) 8710915Sandreas.sandberg@arm.com#define SIDETIM (4) 8810915Sandreas.sandberg@arm.com#define UDMACTL (5) 8910915Sandreas.sandberg@arm.com#define UDMATIM (6) 9010915Sandreas.sandberg@arm.com 9110915Sandreas.sandberg@arm.com// PCI Command bit fields 9210915Sandreas.sandberg@arm.com#define BME 0x04 // Bus master function enable 9310915Sandreas.sandberg@arm.com#define IOSE 0x01 // I/O space enable 9410915Sandreas.sandberg@arm.com 9510915Sandreas.sandberg@arm.comclass IntrControl; 9610915Sandreas.sandberg@arm.comclass IdeDisk; 9710915Sandreas.sandberg@arm.comclass PciConfigAll; 9810915Sandreas.sandberg@arm.comclass Tsunami; 9910915Sandreas.sandberg@arm.comclass PhysicalMemory; 10010915Sandreas.sandberg@arm.comclass BaseInterface; 10110915Sandreas.sandberg@arm.comclass HierParams; 10210915Sandreas.sandberg@arm.comclass Bus; 10310915Sandreas.sandberg@arm.com 10410915Sandreas.sandberg@arm.com/** 10510915Sandreas.sandberg@arm.com * Device model for an Intel PIIX4 IDE controller 10610915Sandreas.sandberg@arm.com */ 10710915Sandreas.sandberg@arm.com 10810915Sandreas.sandberg@arm.comclass IdeController : public PciDev 10910915Sandreas.sandberg@arm.com{ 11010915Sandreas.sandberg@arm.com private: 11110915Sandreas.sandberg@arm.com /** Primary command block registers */ 11210915Sandreas.sandberg@arm.com Addr pri_cmd_addr; 11310915Sandreas.sandberg@arm.com Addr pri_cmd_size; 11410915Sandreas.sandberg@arm.com /** Primary control block registers */ 11510915Sandreas.sandberg@arm.com Addr pri_ctrl_addr; 11610915Sandreas.sandberg@arm.com Addr pri_ctrl_size; 11710915Sandreas.sandberg@arm.com /** Secondary command block registers */ 11810915Sandreas.sandberg@arm.com Addr sec_cmd_addr; 11910915Sandreas.sandberg@arm.com Addr sec_cmd_size; 12010915Sandreas.sandberg@arm.com /** Secondary control block registers */ 12110915Sandreas.sandberg@arm.com Addr sec_ctrl_addr; 12210915Sandreas.sandberg@arm.com Addr sec_ctrl_size; 12310915Sandreas.sandberg@arm.com /** Bus master interface (BMI) registers */ 12410915Sandreas.sandberg@arm.com Addr bmi_addr; 12510915Sandreas.sandberg@arm.com Addr bmi_size; 12610915Sandreas.sandberg@arm.com 12710915Sandreas.sandberg@arm.com private: 12810915Sandreas.sandberg@arm.com /** Registers used for programmed I/O and bus master interface */ 12910915Sandreas.sandberg@arm.com uint8_t regs[40]; 13010915Sandreas.sandberg@arm.com /** Registers used in PCI configuration */ 13110915Sandreas.sandberg@arm.com uint8_t pci_regs[8]; 13210915Sandreas.sandberg@arm.com 13310915Sandreas.sandberg@arm.com // Internal management variables 13410915Sandreas.sandberg@arm.com bool io_enabled; 13510915Sandreas.sandberg@arm.com bool bm_enabled; 13610915Sandreas.sandberg@arm.com bool cmd_in_progress[4]; 13710915Sandreas.sandberg@arm.com 13810915Sandreas.sandberg@arm.com private: 13910915Sandreas.sandberg@arm.com /** Pointer to the chipset */ 14010915Sandreas.sandberg@arm.com Tsunami *tsunami; 14110915Sandreas.sandberg@arm.com /** IDE disks connected to controller */ 14210915Sandreas.sandberg@arm.com IdeDisk *disks[4]; 14310915Sandreas.sandberg@arm.com 14410915Sandreas.sandberg@arm.com private: 14510915Sandreas.sandberg@arm.com /** Get offset into register file from access address */ 14610915Sandreas.sandberg@arm.com Addr getOffset(const Addr &addr) { 14710915Sandreas.sandberg@arm.com Addr offset = addr; 14810915Sandreas.sandberg@arm.com 149 if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) { 150 offset -= pri_cmd_addr; 151 offset += CMD0; 152 } else if (addr >= pri_ctrl_addr && 153 addr < (pri_ctrl_addr + pri_ctrl_size)) { 154 offset -= pri_ctrl_addr; 155 offset += CTRL0; 156 } else if (addr >= sec_cmd_addr && 157 addr < (sec_cmd_addr + sec_cmd_size)) { 158 offset -= sec_cmd_addr; 159 offset += CMD1; 160 } else if (addr >= sec_ctrl_addr && 161 addr < (sec_ctrl_addr + sec_ctrl_size)) { 162 offset -= sec_ctrl_addr; 163 offset += CTRL1; 164 } else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) { 165 offset -= bmi_addr; 166 offset += BMI; 167 } else { 168 panic("IDE controller access to invalid address: %#x\n", addr); 169 } 170 171 return offset; 172 }; 173 /** Select the disk based on the register offset */ 174 int getDisk(const Addr &offset) { 175 int disk = 0; 176 177 // If the offset is in the channel 1 range, disks are 2 or 3 178 if (offset >= CMD1 && offset < BMI && offset >= (BMI + BMIC1)) 179 disk += 2; 180 181 if (disk < 2) { 182 if (regs[CMD0 + IDE_STATUS_OFFSET] & 0x10) 183 disk += 1; 184 } else { 185 if (regs[CMD1 + IDE_STATUS_OFFSET] & 0x10) 186 disk += 1; 187 } 188 189 return disk; 190 }; 191 192 public: 193 /** 194 * Constructs and initializes this controller. 195 * @param name The name of this controller. 196 * @param ic The interrupt controller. 197 * @param mmu The memory controller 198 * @param cf PCI config space 199 * @param cd PCI config data 200 * @param bus_num The PCI bus number 201 * @param dev_num The PCI device number 202 * @param func_num The PCI function number 203 * @param host_bus The host bus to connect to 204 * @param hier The hierarchy parameters 205 */ 206 IdeController(const std::string &name, IntrControl *ic, 207 const vector<IdeDisk *> &new_disks, 208 MemoryController *mmu, PciConfigAll *cf, 209 PciConfigData *cd, Tsunami *t, 210 uint32_t bus_num, uint32_t dev_num, uint32_t func_num, 211 Bus *host_bus, HierParams *hier); 212 213 /** 214 * Deletes the connected devices. 215 */ 216 ~IdeController(); 217 218 virtual void WriteConfig(int offset, int size, uint32_t data); 219 virtual void ReadConfig(int offset, int size, uint8_t *data); 220 221 /** 222 * Read a done field for a given target. 223 * @param req Contains the address of the field to read. 224 * @param data Return the field read. 225 * @return The fault condition of the access. 226 */ 227 virtual Fault read(MemReqPtr &req, uint8_t *data); 228 229 /** 230 * Write to the mmapped I/O control registers. 231 * @param req Contains the address to write to. 232 * @param data The data to write. 233 * @return The fault condition of the access. 234 */ 235 virtual Fault write(MemReqPtr &req, const uint8_t *data); 236 237 /** 238 * Cache access timing specific to device 239 * @param req Memory request 240 */ 241 Tick cacheAccess(MemReqPtr &req); 242 243 /** 244 * Serialize this object to the given output stream. 245 * @param os The stream to serialize to. 246 */ 247 virtual void serialize(std::ostream &os); 248 249 /** 250 * Reconstruct the state of this object from a checkpoint. 251 * @param cp The checkpoint use. 252 * @param section The section name of this object 253 */ 254 virtual void unserialize(Checkpoint *cp, const std::string §ion); 255 256}; 257#endif // __IDE_CTRL_HH_ 258