ide_ctrl.hh revision 5776 
16498Snate@binkert.org/*
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276498Snate@binkert.org *
284479Sbinkertn@umich.edu * Authors: Andrew Schultz
294479Sbinkertn@umich.edu *          Miguel Serrano
304479Sbinkertn@umich.edu */
316498Snate@binkert.org
324479Sbinkertn@umich.edu/** @file
334479Sbinkertn@umich.edu * Simple PCI IDE controller with bus mastering capability and UDMA
344479Sbinkertn@umich.edu * modeled after controller in the Intel PIIX4 chip
354479Sbinkertn@umich.edu */
364479Sbinkertn@umich.edu
374479Sbinkertn@umich.edu#ifndef __IDE_CTRL_HH__
384479Sbinkertn@umich.edu#define __IDE_CTRL_HH__
394479Sbinkertn@umich.edu
404479Sbinkertn@umich.edu#include "base/bitunion.hh"
41#include "dev/pcidev.hh"
42#include "dev/pcireg.h"
43#include "dev/io_device.hh"
44#include "params/IdeController.hh"
45
46class IdeDisk;
47
48/**
49 * Device model for an Intel PIIX4 IDE controller
50 */
51
52class IdeController : public PciDev
53{
54  private:
55    // Bus master IDE status register bit fields
56    BitUnion8(BMIStatusReg)
57        Bitfield<6> dmaCap0;
58        Bitfield<5> dmaCap1;
59        Bitfield<2> intStatus;
60        Bitfield<1> dmaError;
61        Bitfield<0> active;
62    EndBitUnion(BMIStatusReg)
63
64    BitUnion8(BMICommandReg)
65        Bitfield<3> rw;
66        Bitfield<0> startStop;
67    EndBitUnion(BMICommandReg)
68
69    struct Channel
70    {
71        std::string _name;
72
73        const std::string
74        name()
75        {
76            return _name;
77        }
78
79        /** Command and control block registers */
80        Addr cmdAddr, cmdSize, ctrlAddr, ctrlSize;
81
82        /** Registers used for bus master interface */
83        struct BMIRegs
84        {
85            BMICommandReg command;
86            uint8_t reserved0;
87            BMIStatusReg status;
88            uint8_t reserved1;
89            uint32_t bmidtp;
90        } bmiRegs;
91
92        /** IDE disks connected to this controller */
93        IdeDisk *master, *slave;
94
95        /** Currently selected disk */
96        IdeDisk *selected;
97
98        bool selectBit;
99
100        void
101        select(bool selSlave)
102        {
103            selectBit = selSlave;
104            selected = selectBit ? slave : master;
105        }
106
107        void accessCommand(Addr offset, int size, uint8_t *data, bool read);
108        void accessControl(Addr offset, int size, uint8_t *data, bool read);
109        void accessBMI(Addr offset, int size, uint8_t *data, bool read);
110
111        Channel(std::string newName, Addr _cmdSize, Addr _ctrlSize);
112        ~Channel();
113
114        void serialize(const std::string &base, std::ostream &os);
115        void unserialize(const std::string &base, Checkpoint *cp,
116            const std::string &section);
117    };
118
119    Channel primary;
120    Channel secondary;
121
122    /** Bus master interface (BMI) registers */
123    Addr bmiAddr, bmiSize;
124
125    /** Registers used in device specific PCI configuration */
126    uint16_t primaryTiming, secondaryTiming;
127    uint8_t deviceTiming;
128    uint8_t udmaControl;
129    uint16_t udmaTiming;
130    uint16_t ideConfig;
131
132    // Internal management variables
133    bool ioEnabled;
134    bool bmEnabled;
135
136    void dispatchAccess(PacketPtr pkt, bool read);
137
138  public:
139    typedef IdeControllerParams Params;
140    const Params *params() const { return (const Params *)_params; }
141    IdeController(Params *p);
142
143    /** See if a disk is selected based on its pointer */
144    bool isDiskSelected(IdeDisk *diskPtr);
145
146    void intrPost();
147
148    Tick writeConfig(PacketPtr pkt);
149    Tick readConfig(PacketPtr pkt);
150
151    void setDmaComplete(IdeDisk *disk);
152
153    Tick read(PacketPtr pkt);
154    Tick write(PacketPtr pkt);
155
156    void serialize(std::ostream &os);
157    void unserialize(Checkpoint *cp, const std::string &section);
158};
159#endif // __IDE_CTRL_HH_
160