ide_ctrl.hh revision 11169
12SN/A/* 213590Srekai.gonzalezalberquilla@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 313429Srekai.gonzalezalberquilla@arm.com * All rights reserved. 413429Srekai.gonzalezalberquilla@arm.com * 513429Srekai.gonzalezalberquilla@arm.com * Redistribution and use in source and binary forms, with or without 613429Srekai.gonzalezalberquilla@arm.com * modification, are permitted provided that the following conditions are 713429Srekai.gonzalezalberquilla@arm.com * met: redistributions of source code must retain the above copyright 813429Srekai.gonzalezalberquilla@arm.com * notice, this list of conditions and the following disclaimer; 913429Srekai.gonzalezalberquilla@arm.com * redistributions in binary form must reproduce the above copyright 1013429Srekai.gonzalezalberquilla@arm.com * notice, this list of conditions and the following disclaimer in the 1113429Srekai.gonzalezalberquilla@arm.com * documentation and/or other materials provided with the distribution; 1213429Srekai.gonzalezalberquilla@arm.com * neither the name of the copyright holders nor the names of its 1313429Srekai.gonzalezalberquilla@arm.com * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A * 282SN/A * Authors: Andrew Schultz 292SN/A * Miguel Serrano 302SN/A */ 312SN/A 322SN/A/** @file 332SN/A * Simple PCI IDE controller with bus mastering capability and UDMA 342SN/A * modeled after controller in the Intel PIIX4 chip 352SN/A */ 362SN/A 372SN/A#ifndef __IDE_CTRL_HH__ 382SN/A#define __IDE_CTRL_HH__ 392665Ssaidi@eecs.umich.edu 402665Ssaidi@eecs.umich.edu#include "base/bitunion.hh" 412SN/A#include "dev/io_device.hh" 422SN/A#include "dev/pcidev.hh" 433877Sbinkertn@umich.edu#include "dev/pcireg.h" 443877Sbinkertn@umich.edu#include "params/IdeController.hh" 452147SN/A 4613429Srekai.gonzalezalberquilla@arm.comclass IdeDisk; 4713429Srekai.gonzalezalberquilla@arm.com 488221Snate@binkert.org/** 498221Snate@binkert.org * Device model for an Intel PIIX4 IDE controller 508221Snate@binkert.org */ 518221Snate@binkert.org 528221Snate@binkert.orgclass IdeController : public PciDevice 538221Snate@binkert.org{ 548221Snate@binkert.org private: 558221Snate@binkert.org // Bus master IDE status register bit fields 568221Snate@binkert.org BitUnion8(BMIStatusReg) 578221Snate@binkert.org Bitfield<6> dmaCap0; 588221Snate@binkert.org Bitfield<5> dmaCap1; 592SN/A Bitfield<2> intStatus; 602SN/A Bitfield<1> dmaError; 612SN/A Bitfield<0> active; 628221Snate@binkert.org EndBitUnion(BMIStatusReg) 638221Snate@binkert.org 648221Snate@binkert.org BitUnion8(BMICommandReg) 658221Snate@binkert.org Bitfield<3> rw; 667866Snate@binkert.org Bitfield<0> startStop; 672SN/A EndBitUnion(BMICommandReg) 682SN/A 697057Snate@binkert.org struct Channel 707057Snate@binkert.org { 717057Snate@binkert.org std::string _name; 722SN/A 737057Snate@binkert.org const std::string 742SN/A name() 752SN/A { 768221Snate@binkert.org return _name; 778221Snate@binkert.org } 788221Snate@binkert.org 798221Snate@binkert.org /** Command and control block registers */ 808221Snate@binkert.org Addr cmdAddr, cmdSize, ctrlAddr, ctrlSize; 818221Snate@binkert.org 828221Snate@binkert.org /** Registers used for bus master interface */ 832SN/A struct BMIRegs 848221Snate@binkert.org { 858221Snate@binkert.org BMICommandReg command; 868221Snate@binkert.org uint8_t reserved0; 878221Snate@binkert.org BMIStatusReg status; 888221Snate@binkert.org uint8_t reserved1; 898221Snate@binkert.org uint32_t bmidtp; 908221Snate@binkert.org } bmiRegs; 918221Snate@binkert.org 928221Snate@binkert.org /** IDE disks connected to this controller */ 938221Snate@binkert.org IdeDisk *master, *slave; 942SN/A 952SN/A /** Currently selected disk */ 968221Snate@binkert.org IdeDisk *selected; 9713429Srekai.gonzalezalberquilla@arm.com 988221Snate@binkert.org bool selectBit; 998221Snate@binkert.org 1008221Snate@binkert.org void 10113429Srekai.gonzalezalberquilla@arm.com select(bool selSlave) 1022SN/A { 1032SN/A selectBit = selSlave; 1048221Snate@binkert.org selected = selectBit ? slave : master; 1058221Snate@binkert.org } 1068221Snate@binkert.org 1078221Snate@binkert.org void accessCommand(Addr offset, int size, uint8_t *data, bool read); 1088221Snate@binkert.org void accessControl(Addr offset, int size, uint8_t *data, bool read); 1098221Snate@binkert.org void accessBMI(Addr offset, int size, uint8_t *data, bool read); 1108221Snate@binkert.org 1118221Snate@binkert.org Channel(std::string newName, Addr _cmdSize, Addr _ctrlSize); 1128221Snate@binkert.org ~Channel(); 1138221Snate@binkert.org 1148221Snate@binkert.org void serialize(const std::string &base, std::ostream &os) const; 1158221Snate@binkert.org void unserialize(const std::string &base, CheckpointIn &cp); 1168221Snate@binkert.org }; 1178221Snate@binkert.org 1188221Snate@binkert.org Channel primary; 1192SN/A Channel secondary; 1202SN/A 1212SN/A /** Bus master interface (BMI) registers */ 12213474Sgiacomo.gabrielli@arm.com Addr bmiAddr, bmiSize; 12313474Sgiacomo.gabrielli@arm.com 12413474Sgiacomo.gabrielli@arm.com /** Registers used in device specific PCI configuration */ 1251078SN/A uint16_t primaryTiming, secondaryTiming; 12613429Srekai.gonzalezalberquilla@arm.com uint8_t deviceTiming; 12713429Srekai.gonzalezalberquilla@arm.com uint8_t udmaControl; 12813429Srekai.gonzalezalberquilla@arm.com uint16_t udmaTiming; 12913429Srekai.gonzalezalberquilla@arm.com uint16_t ideConfig; 13013429Srekai.gonzalezalberquilla@arm.com 13113429Srekai.gonzalezalberquilla@arm.com // Internal management variables 13213429Srekai.gonzalezalberquilla@arm.com bool ioEnabled; 13313429Srekai.gonzalezalberquilla@arm.com bool bmEnabled; 13413429Srekai.gonzalezalberquilla@arm.com 13513429Srekai.gonzalezalberquilla@arm.com uint32_t ioShift, ctrlOffset; 13613429Srekai.gonzalezalberquilla@arm.com 13713429Srekai.gonzalezalberquilla@arm.com void dispatchAccess(PacketPtr pkt, bool read); 1388221Snate@binkert.org 1398221Snate@binkert.org public: 1402SN/A typedef IdeControllerParams Params; 1412SN/A const Params *params() const { return (const Params *)_params; } 1428221Snate@binkert.org IdeController(Params *p); 1438221Snate@binkert.org 1448221Snate@binkert.org /** See if a disk is selected based on its pointer */ 1458221Snate@binkert.org bool isDiskSelected(IdeDisk *diskPtr); 1468221Snate@binkert.org 1478221Snate@binkert.org void intrPost(); 1488221Snate@binkert.org 1498221Snate@binkert.org Tick writeConfig(PacketPtr pkt) override; 1501114SN/A Tick readConfig(PacketPtr pkt) override; 1512SN/A 1522SN/A void setDmaComplete(IdeDisk *disk); 1532SN/A 1542SN/A Tick read(PacketPtr pkt) override; 1558221Snate@binkert.org Tick write(PacketPtr pkt) override; 1568221Snate@binkert.org 1578221Snate@binkert.org void serialize(CheckpointOut &cp) const override; 1588221Snate@binkert.org void unserialize(CheckpointIn &cp) override; 1598221Snate@binkert.org}; 1608221Snate@binkert.org#endif // __IDE_CTRL_HH_ 1618221Snate@binkert.org