14486SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan
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264486SN/A#
274486SN/A# Authors: Nathan Binkert
284486SN/A
293102SN/Afrom m5.SimObject import SimObject
303102SN/Afrom m5.params import *
3113665Sandreas.sandberg@arm.comfrom m5.objects.PciDevice import PciDevice
321310SN/A
331427SN/Aclass IdeID(Enum): vals = ['master', 'slave']
341310SN/A
354982SN/Aclass IdeDisk(SimObject):
364982SN/A    type = 'IdeDisk'
3711264Sandreas.sandberg@arm.com    cxx_header = "dev/storage/ide_disk.hh"
384982SN/A    delay = Param.Latency('1us', "Fixed disk delay in microseconds")
394982SN/A    driveID = Param.IdeID('master', "Drive ID")
404982SN/A    image = Param.DiskImage("Disk image")
414982SN/A
424982SN/Aclass IdeController(PciDevice):
434982SN/A    type = 'IdeController'
4411264Sandreas.sandberg@arm.com    cxx_header = "dev/storage/ide_ctrl.hh"
454982SN/A    disks = VectorParam.IdeDisk("IDE disks attached to this controller")
464982SN/A
472916SN/A    VendorID = 0x8086
482916SN/A    DeviceID = 0x7111
492916SN/A    Command = 0x0
502916SN/A    Status = 0x280
512916SN/A    Revision = 0x0
522916SN/A    ClassCode = 0x01
532916SN/A    SubClassCode = 0x01
542916SN/A    ProgIF = 0x85
552916SN/A    BAR0 = 0x00000001
562916SN/A    BAR1 = 0x00000001
572916SN/A    BAR2 = 0x00000001
582916SN/A    BAR3 = 0x00000001
592916SN/A    BAR4 = 0x00000001
602916SN/A    BAR5 = 0x00000001
612916SN/A    InterruptLine = 0x1f
622916SN/A    InterruptPin = 0x01
632916SN/A    BAR0Size = '8B'
642916SN/A    BAR1Size = '4B'
652916SN/A    BAR2Size = '8B'
662916SN/A    BAR3Size = '4B'
672916SN/A    BAR4Size = '16B'
682916SN/A
697750SN/A    io_shift = Param.UInt32(0x0, "IO port shift");
707750SN/A    ctrl_offset = Param.UInt32(0x0, "IDE disk control offset")
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