t1000.cc revision 11793:ef606668d247
12391SN/A/* 210482Sandreas.hansson@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 37733SAli.Saidi@ARM.com * All rights reserved. 47733SAli.Saidi@ARM.com * 57733SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67733SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77733SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87733SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97733SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107733SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117733SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127733SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137733SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 142391SN/A * this software without specific prior written permission. 152391SN/A * 162391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272391SN/A * 282391SN/A * Authors: Ali Saidi 292391SN/A */ 302391SN/A 312391SN/A/** @file 322391SN/A * Implementation of T1000 platform. 332391SN/A */ 342391SN/A 352391SN/A#include "dev/sparc/t1000.hh" 362665Ssaidi@eecs.umich.edu 378931Sandreas.hansson@arm.com#include <deque> 382391SN/A#include <string> 392391SN/A#include <vector> 4011793Sbrandon.potter@amd.com 4111793Sbrandon.potter@amd.com#include "config/the_isa.hh" 4211793Sbrandon.potter@amd.com#include "cpu/intr_control.hh" 439293Sandreas.hansson@arm.com#include "dev/terminal.hh" 449293Sandreas.hansson@arm.com#include "sim/system.hh" 459293Sandreas.hansson@arm.com 469293Sandreas.hansson@arm.comusing namespace std; 479293Sandreas.hansson@arm.com//Should this be AlphaISA? 489293Sandreas.hansson@arm.comusing namespace TheISA; 499293Sandreas.hansson@arm.com 509293Sandreas.hansson@arm.comT1000::T1000(const Params *p) 519293Sandreas.hansson@arm.com : Platform(p), system(p->system) 529293Sandreas.hansson@arm.com{} 539293Sandreas.hansson@arm.com 549293Sandreas.hansson@arm.comvoid 559356Snilay@cs.wisc.eduT1000::postConsoleInt() 5610405Sandreas.hansson@arm.com{ 579293Sandreas.hansson@arm.com warn_once("Don't know what interrupt to post for console.\n"); 589293Sandreas.hansson@arm.com //panic("Need implementation\n"); 592394SN/A} 6010700Sandreas.hansson@arm.com 6110700Sandreas.hansson@arm.comvoid 6210700Sandreas.hansson@arm.comT1000::clearConsoleInt() 6311446Sbaz21@cam.ac.uk{ 6411446Sbaz21@cam.ac.uk warn_once("Don't know what interrupt to clear for console.\n"); 6510700Sandreas.hansson@arm.com //panic("Need implementation\n"); 6611446Sbaz21@cam.ac.uk} 6710700Sandreas.hansson@arm.com 6810700Sandreas.hansson@arm.comvoid 6910700Sandreas.hansson@arm.comT1000::postPciInt(int line) 7010700Sandreas.hansson@arm.com{ 7110700Sandreas.hansson@arm.com panic("Need implementation\n"); 722391SN/A} 732391SN/A 749293Sandreas.hansson@arm.comvoid 7510700Sandreas.hansson@arm.comT1000::clearPciInt(int line) 7610700Sandreas.hansson@arm.com{ 7710700Sandreas.hansson@arm.com panic("Need implementation\n"); 7810700Sandreas.hansson@arm.com} 792391SN/A 8010700Sandreas.hansson@arm.comAddr 8110700Sandreas.hansson@arm.comT1000::pciToDma(Addr pciAddr) const 8210700Sandreas.hansson@arm.com{ 839293Sandreas.hansson@arm.com panic("Need implementation\n"); 849293Sandreas.hansson@arm.com M5_DUMMY_RETURN 8510482Sandreas.hansson@arm.com} 868931Sandreas.hansson@arm.com 8710482Sandreas.hansson@arm.com 8810482Sandreas.hansson@arm.comAddr 892391SN/AT1000::calcPciConfigAddr(int bus, int dev, int func) 908931Sandreas.hansson@arm.com{ 9110482Sandreas.hansson@arm.com panic("Need implementation\n"); 928931Sandreas.hansson@arm.com M5_DUMMY_RETURN 938931Sandreas.hansson@arm.com} 948931Sandreas.hansson@arm.com 9510482Sandreas.hansson@arm.comAddr 9610482Sandreas.hansson@arm.comT1000::calcPciIOAddr(Addr addr) 9710482Sandreas.hansson@arm.com{ 989293Sandreas.hansson@arm.com panic("Need implementation\n"); 999293Sandreas.hansson@arm.com M5_DUMMY_RETURN 1009293Sandreas.hansson@arm.com} 1019293Sandreas.hansson@arm.com 10210482Sandreas.hansson@arm.comAddr 10310482Sandreas.hansson@arm.comT1000::calcPciMemAddr(Addr addr) 10410482Sandreas.hansson@arm.com{ 10510482Sandreas.hansson@arm.com panic("Need implementation\n"); 10610482Sandreas.hansson@arm.com M5_DUMMY_RETURN 10710482Sandreas.hansson@arm.com} 10810482Sandreas.hansson@arm.com 10910482Sandreas.hansson@arm.comT1000 * 1109293Sandreas.hansson@arm.comT1000Params::create() 1119293Sandreas.hansson@arm.com{ 1129293Sandreas.hansson@arm.com return new T1000(this); 1139293Sandreas.hansson@arm.com} 11410482Sandreas.hansson@arm.com