iob.hh revision 9090
14104Ssaidi@eecs.umich.edu/* 24104Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 34104Ssaidi@eecs.umich.edu * All rights reserved. 44104Ssaidi@eecs.umich.edu * 54104Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64104Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 74104Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84104Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94104Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104104Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114104Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124104Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134104Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144104Ssaidi@eecs.umich.edu * this software without specific prior written permission. 154104Ssaidi@eecs.umich.edu * 164104Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174104Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184104Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194104Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204104Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214104Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224104Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234104Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244104Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254104Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264104Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274104Ssaidi@eecs.umich.edu * 284104Ssaidi@eecs.umich.edu * Authors: Ali Saidi 294104Ssaidi@eecs.umich.edu */ 304104Ssaidi@eecs.umich.edu 314104Ssaidi@eecs.umich.edu/** @file 324104Ssaidi@eecs.umich.edu * This device implements the niagara I/O Bridge chip. The device manages 334104Ssaidi@eecs.umich.edu * internal (ipi) and external (serial, pci via jbus). 344104Ssaidi@eecs.umich.edu */ 354104Ssaidi@eecs.umich.edu 364104Ssaidi@eecs.umich.edu#ifndef __DEV_SPARC_IOB_HH__ 374104Ssaidi@eecs.umich.edu#define __DEV_SPARC_IOB_HH__ 384104Ssaidi@eecs.umich.edu 394104Ssaidi@eecs.umich.edu#include "base/range.hh" 408229Snate@binkert.org#include "dev/disk_image.hh" 414104Ssaidi@eecs.umich.edu#include "dev/io_device.hh" 424762Snate@binkert.org#include "params/Iob.hh" 434104Ssaidi@eecs.umich.edu 444104Ssaidi@eecs.umich.educlass IntrControl; 454104Ssaidi@eecs.umich.edu 464104Ssaidi@eecs.umich.educonst int MaxNiagaraProcs = 32; 474104Ssaidi@eecs.umich.edu// IOB Managment Addresses 484104Ssaidi@eecs.umich.educonst Addr IntManAddr = 0x0000; 494104Ssaidi@eecs.umich.educonst Addr IntManSize = 0x0020; 504104Ssaidi@eecs.umich.educonst Addr IntCtlAddr = 0x0400; 514104Ssaidi@eecs.umich.educonst Addr IntCtlSize = 0x0020; 524104Ssaidi@eecs.umich.educonst Addr JIntVecAddr = 0x0A00; 534104Ssaidi@eecs.umich.educonst Addr IntVecDisAddr = 0x0800; 544104Ssaidi@eecs.umich.educonst Addr IntVecDisSize = 0x0100; 554104Ssaidi@eecs.umich.edu 564104Ssaidi@eecs.umich.edu 574104Ssaidi@eecs.umich.edu// IOB Control Addresses 584104Ssaidi@eecs.umich.educonst Addr JIntData0Addr = 0x0400; 594104Ssaidi@eecs.umich.educonst Addr JIntData1Addr = 0x0500; 604104Ssaidi@eecs.umich.educonst Addr JIntDataA0Addr = 0x0600; 614104Ssaidi@eecs.umich.educonst Addr JIntDataA1Addr = 0x0700; 624104Ssaidi@eecs.umich.educonst Addr JIntBusyAddr = 0x0900; 634104Ssaidi@eecs.umich.educonst Addr JIntBusySize = 0x0100; 644104Ssaidi@eecs.umich.educonst Addr JIntABusyAddr = 0x0B00; 654104Ssaidi@eecs.umich.edu 664104Ssaidi@eecs.umich.edu 674104Ssaidi@eecs.umich.edu// IOB Masks 684104Ssaidi@eecs.umich.educonst uint64_t IntManMask = 0x01F3F; 694104Ssaidi@eecs.umich.educonst uint64_t IntCtlMask = 0x00006; 704104Ssaidi@eecs.umich.educonst uint64_t JIntVecMask = 0x0003F; 714104Ssaidi@eecs.umich.educonst uint64_t IntVecDis = 0x31F3F; 724104Ssaidi@eecs.umich.educonst uint64_t JIntBusyMask = 0x0003F; 734104Ssaidi@eecs.umich.edu 744104Ssaidi@eecs.umich.edu 754104Ssaidi@eecs.umich.educlass Iob : public PioDevice 764104Ssaidi@eecs.umich.edu{ 774104Ssaidi@eecs.umich.edu private: 784104Ssaidi@eecs.umich.edu IntrControl *ic; 794104Ssaidi@eecs.umich.edu Addr iobManAddr; 804104Ssaidi@eecs.umich.edu Addr iobManSize; 814104Ssaidi@eecs.umich.edu Addr iobJBusAddr; 824104Ssaidi@eecs.umich.edu Addr iobJBusSize; 834104Ssaidi@eecs.umich.edu Tick pioDelay; 844104Ssaidi@eecs.umich.edu 854104Ssaidi@eecs.umich.edu enum DeviceId { 864104Ssaidi@eecs.umich.edu Interal = 0, 874104Ssaidi@eecs.umich.edu Error = 1, 884104Ssaidi@eecs.umich.edu SSI = 2, 894104Ssaidi@eecs.umich.edu Reserved = 3, 904104Ssaidi@eecs.umich.edu NumDeviceIds 914104Ssaidi@eecs.umich.edu }; 924104Ssaidi@eecs.umich.edu 934104Ssaidi@eecs.umich.edu struct IntMan { 944104Ssaidi@eecs.umich.edu int cpu; 954104Ssaidi@eecs.umich.edu int vector; 964104Ssaidi@eecs.umich.edu }; 974104Ssaidi@eecs.umich.edu 984104Ssaidi@eecs.umich.edu struct IntCtl { 994104Ssaidi@eecs.umich.edu bool mask; 1004104Ssaidi@eecs.umich.edu bool pend; 1014104Ssaidi@eecs.umich.edu }; 1024104Ssaidi@eecs.umich.edu 1034104Ssaidi@eecs.umich.edu struct IntBusy { 1044104Ssaidi@eecs.umich.edu bool busy; 1054104Ssaidi@eecs.umich.edu int source; 1064104Ssaidi@eecs.umich.edu }; 1074104Ssaidi@eecs.umich.edu 1084104Ssaidi@eecs.umich.edu enum Type { 1094104Ssaidi@eecs.umich.edu Interrupt, 1104104Ssaidi@eecs.umich.edu Reset, 1114104Ssaidi@eecs.umich.edu Idle, 1124104Ssaidi@eecs.umich.edu Resume 1134104Ssaidi@eecs.umich.edu }; 1144104Ssaidi@eecs.umich.edu 1154104Ssaidi@eecs.umich.edu IntMan intMan[NumDeviceIds]; 1164104Ssaidi@eecs.umich.edu IntCtl intCtl[NumDeviceIds]; 1174104Ssaidi@eecs.umich.edu uint64_t jIntVec; 1184104Ssaidi@eecs.umich.edu uint64_t jBusData0[MaxNiagaraProcs]; 1194104Ssaidi@eecs.umich.edu uint64_t jBusData1[MaxNiagaraProcs]; 1204104Ssaidi@eecs.umich.edu IntBusy jIntBusy[MaxNiagaraProcs]; 1214104Ssaidi@eecs.umich.edu 1224104Ssaidi@eecs.umich.edu void writeIob(PacketPtr pkt); 1234104Ssaidi@eecs.umich.edu void writeJBus(PacketPtr pkt); 1244104Ssaidi@eecs.umich.edu void readIob(PacketPtr pkt); 1254104Ssaidi@eecs.umich.edu void readJBus(PacketPtr pkt); 1264104Ssaidi@eecs.umich.edu 1274762Snate@binkert.org public: 1284762Snate@binkert.org typedef IobParams Params; 1294762Snate@binkert.org Iob(const Params *p); 1304104Ssaidi@eecs.umich.edu 1314762Snate@binkert.org const Params * 1324762Snate@binkert.org params() const 1334104Ssaidi@eecs.umich.edu { 1344762Snate@binkert.org return dynamic_cast<const Params *>(_params); 1354762Snate@binkert.org } 1364104Ssaidi@eecs.umich.edu 1374104Ssaidi@eecs.umich.edu virtual Tick read(PacketPtr pkt); 1384104Ssaidi@eecs.umich.edu virtual Tick write(PacketPtr pkt); 1394104Ssaidi@eecs.umich.edu void generateIpi(Type type, int cpu_id, int vector); 1404104Ssaidi@eecs.umich.edu void receiveDeviceInterrupt(DeviceId devid); 1414762Snate@binkert.org bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, 1424762Snate@binkert.org uint64_t d1); 1434104Ssaidi@eecs.umich.edu 1449090Sandreas.hansson@arm.com AddrRangeList getAddrRanges() const; 1454104Ssaidi@eecs.umich.edu 1464104Ssaidi@eecs.umich.edu virtual void serialize(std::ostream &os); 1474104Ssaidi@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1484104Ssaidi@eecs.umich.edu 1494104Ssaidi@eecs.umich.edu}; 1504104Ssaidi@eecs.umich.edu 1514104Ssaidi@eecs.umich.edu#endif //__DEV_SPARC_IOB_HH__ 1524104Ssaidi@eecs.umich.edu 153