iob.cc revision 4104 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/** @file
32 * This device implemetns the niagara I/O bridge chip. It manages incomming
33 * interrupts and posts them to the CPU when needed. It holds mask registers and
34 * various status registers for CPUs to check what interrupts are pending as
35 * well as facilities to send IPIs to other cpus.
36 */
37
38#include <cstring>
39
40#include "arch/sparc/isa_traits.hh"
41#include "base/trace.hh"
42#include "cpu/intr_control.hh"
43#include "dev/sparc/iob.hh"
44#include "dev/platform.hh"
45#include "mem/port.hh"
46#include "mem/packet_access.hh"
47#include "sim/builder.hh"
48#include "sim/system.hh"
49
50Iob::Iob(Params *p)
51    : PioDevice(p), ic(p->platform->intrctrl)
52{
53    iobManAddr = ULL(0x9800000000);
54    iobManSize = ULL(0x0100000000);
55    iobJBusAddr = ULL(0x9F00000000);
56    iobJBusSize = ULL(0x0100000000);
57    assert (params()->system->threadContexts.size() <= MaxNiagaraProcs);
58    // Get the interrupt controller from the platform
59    ic = platform->intrctrl;
60
61    for (int x = 0; x < NumDeviceIds; ++x) {
62        intMan[x].cpu = 0;
63        intMan[x].vector = 0;
64        intCtl[x].mask = true;
65        intCtl[x].pend = false;
66    }
67
68}
69
70Tick
71Iob::read(PacketPtr pkt)
72{
73    assert(pkt->result == Packet::Unknown);
74
75    if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize)
76        readIob(pkt);
77    else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize)
78        readJBus(pkt);
79    else
80        panic("Invalid address reached Iob\n");
81
82    pkt->result = Packet::Success;
83    return pioDelay;
84}
85
86void
87Iob::readIob(PacketPtr pkt)
88{
89        Addr accessAddr = pkt->getAddr() - iobManAddr;
90        int index;
91        uint64_t data;
92
93        if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) {
94            index = (accessAddr - IntManAddr) >> 3;
95            data = intMan[index].cpu << 8 | intMan[index].vector << 0;
96            pkt->set(data);
97            return;
98        }
99
100        if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
101            index = (accessAddr - IntManAddr) >> 3;
102            data = intCtl[index].mask  ? 1 << 2 : 0 |
103                   intCtl[index].pend  ? 1 << 0 : 0;
104            pkt->set(data);
105            return;
106        }
107
108        if (accessAddr == JIntVecAddr) {
109            pkt->set(jIntVec);
110            return;
111        }
112
113        panic("Read to unknown IOB offset 0x%x\n", accessAddr);
114}
115
116void
117Iob::readJBus(PacketPtr pkt)
118{
119        Addr accessAddr = pkt->getAddr() - iobJBusAddr;
120        int cpuid = pkt->req->getCpuNum();
121        int index;
122        uint64_t data;
123
124
125
126
127        if (accessAddr >= JIntData0Addr && accessAddr < JIntData1Addr) {
128            index = (accessAddr - JIntData0Addr) >> 3;
129            pkt->set(jBusData0[index]);
130            return;
131        }
132
133        if (accessAddr >= JIntData1Addr && accessAddr < JIntDataA0Addr) {
134            index = (accessAddr - JIntData1Addr) >> 3;
135            pkt->set(jBusData1[index]);
136            return;
137        }
138
139        if (accessAddr == JIntDataA0Addr) {
140            pkt->set(jBusData0[cpuid]);
141            return;
142        }
143
144        if (accessAddr == JIntDataA1Addr) {
145            pkt->set(jBusData1[cpuid]);
146            return;
147        }
148
149        if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) {
150            index = (accessAddr - JIntBusyAddr) >> 3;
151            data = jIntBusy[index].busy ? 1 << 5 : 0 |
152                   jIntBusy[index].source;
153            pkt->set(data);
154            return;
155        }
156        if (accessAddr == JIntABusyAddr) {
157            data = jIntBusy[cpuid].busy ? 1 << 5 : 0 |
158                   jIntBusy[cpuid].source;
159            pkt->set(data);
160            return;
161        };
162
163        panic("Read to unknown JBus offset 0x%x\n", accessAddr);
164}
165
166Tick
167Iob::write(PacketPtr pkt)
168{
169    if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize)
170        writeIob(pkt);
171    else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize)
172        writeJBus(pkt);
173    else
174        panic("Invalid address reached Iob\n");
175
176
177    pkt->result = Packet::Success;
178    return pioDelay;
179}
180
181void
182Iob::writeIob(PacketPtr pkt)
183{
184        Addr accessAddr = pkt->getAddr() - iobManAddr;
185        int index;
186        uint64_t data;
187
188        if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) {
189            index = (accessAddr - IntManAddr) >> 3;
190            data = pkt->get<uint64_t>();
191            intMan[index].cpu = bits(data,12,8);
192            intMan[index].vector = bits(data,5,0);
193            return;
194        }
195
196        if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
197            index = (accessAddr - IntManAddr) >> 3;
198            data = pkt->get<uint64_t>();
199            intCtl[index].mask = bits(data,2,2);
200            if (bits(data,1,1))
201                intCtl[index].pend = false;
202            return;
203        }
204
205        if (accessAddr == JIntVecAddr) {
206            jIntVec = bits(pkt->get<uint64_t>(), 5,0);
207            return;
208        }
209
210        if (accessAddr >= IntVecDisAddr && accessAddr < IntVecDisAddr + IntVecDisSize) {
211            Type type;
212            int cpu_id;
213            int vector;
214            index = (accessAddr - IntManAddr) >> 3;
215            data = pkt->get<uint64_t>();
216            type = (Type)bits(data,17,16);
217            cpu_id = bits(data, 12,8);
218            vector = bits(data,5,0);
219            generateIpi(type,cpu_id, vector);
220            return;
221        }
222
223        panic("Write to unknown IOB offset 0x%x\n", accessAddr);
224}
225
226void
227Iob::writeJBus(PacketPtr pkt)
228{
229        Addr accessAddr = pkt->getAddr() - iobJBusAddr;
230        int cpuid = pkt->req->getCpuNum();
231        int index;
232        uint64_t data;
233
234        if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) {
235            index = (accessAddr - JIntBusyAddr) >> 3;
236            data = pkt->get<uint64_t>();
237            jIntBusy[index].busy = bits(data,5,5);
238            return;
239        }
240        if (accessAddr == JIntABusyAddr) {
241            data = pkt->get<uint64_t>();
242            jIntBusy[cpuid].busy = bits(data,5,5);
243            return;
244        };
245
246        panic("Write to unknown JBus offset 0x%x\n", accessAddr);
247}
248
249void
250Iob::receiveDeviceInterrupt(DeviceId devid)
251{
252    assert(devid < NumDeviceIds);
253    if (intCtl[devid].mask)
254        return;
255    intCtl[devid].mask = true;
256    intCtl[devid].pend = true;
257    ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector);
258}
259
260
261void
262Iob::generateIpi(Type type, int cpu_id, int vector)
263{
264    // Only handle interrupts for the moment... Cpu Idle/reset/resume will be
265    // later
266    if (type != 0) {
267        warn("Ignoring IntVecDis write\n");
268        return;
269    }
270    assert(type == 0);
271    ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
272}
273
274bool
275Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1)
276{
277    // If we are already dealing with an interrupt for that cpu we can't deal
278    // with another one right now... come back later
279    if (jIntBusy[cpu_id].busy)
280        return false;
281
282    jIntBusy[cpu_id].busy = true;
283    jIntBusy[cpu_id].source = source;
284    jBusData0[cpu_id] = d0;
285    jBusData1[cpu_id] = d1;
286
287    ic->post(cpu_id, SparcISA::IT_INT_VEC, jIntVec);
288    return true;
289}
290
291void
292Iob::addressRanges(AddrRangeList &range_list)
293{
294    range_list.clear();
295    range_list.push_back(RangeSize(iobManAddr, iobManSize));
296    range_list.push_back(RangeSize(iobJBusAddr, iobJBusSize));
297}
298
299
300void
301Iob::serialize(std::ostream &os)
302{
303
304    SERIALIZE_SCALAR(jIntVec);
305    SERIALIZE_ARRAY(jBusData0, MaxNiagaraProcs);
306    SERIALIZE_ARRAY(jBusData1, MaxNiagaraProcs);
307    for (int x = 0; x < NumDeviceIds; x++) {
308        nameOut(os, csprintf("%s.Int%d", name(), x));
309        paramOut(os, "cpu", intMan[x].cpu);
310        paramOut(os, "vector", intMan[x].vector);
311        paramOut(os, "mask", intCtl[x].mask);
312        paramOut(os, "pend", intCtl[x].pend);
313    };
314    for (int x = 0; x < MaxNiagaraProcs; x++) {
315        nameOut(os, csprintf("%s.jIntBusy%d", name(), x));
316        paramOut(os, "busy", jIntBusy[x].busy);
317        paramOut(os, "source", jIntBusy[x].source);
318    };
319}
320
321void
322Iob::unserialize(Checkpoint *cp, const std::string &section)
323{
324    UNSERIALIZE_SCALAR(jIntVec);
325    UNSERIALIZE_ARRAY(jBusData0, MaxNiagaraProcs);
326    UNSERIALIZE_ARRAY(jBusData1, MaxNiagaraProcs);
327    for (int x = 0; x < NumDeviceIds; x++) {
328        paramIn(cp, csprintf("%s.Int%d", name(), x), "cpu", intMan[x].cpu);
329        paramIn(cp, csprintf("%s.Int%d", name(), x), "vector", intMan[x].vector);
330        paramIn(cp, csprintf("%s.Int%d", name(), x), "mask", intCtl[x].mask);
331        paramIn(cp, csprintf("%s.Int%d", name(), x), "pend", intCtl[x].pend);
332    };
333    for (int x = 0; x < MaxNiagaraProcs; x++) {
334        paramIn(cp, csprintf("%s.jIntBusy%d", name(), x), "busy", jIntBusy[x].busy);
335        paramIn(cp, csprintf("%s.jIntBusy%d", name(), x), "source", jIntBusy[x].source);
336    };
337}
338
339
340
341
342BEGIN_DECLARE_SIM_OBJECT_PARAMS(Iob)
343    Param<Tick> pio_latency;
344    SimObjectParam<Platform *> platform;
345    SimObjectParam<System *> system;
346END_DECLARE_SIM_OBJECT_PARAMS(Iob)
347
348BEGIN_INIT_SIM_OBJECT_PARAMS(Iob)
349
350    INIT_PARAM(pio_latency, "Programmed IO latency"),
351    INIT_PARAM(platform, "platform"),
352    INIT_PARAM(system, "system object")
353
354END_INIT_SIM_OBJECT_PARAMS(Iob)
355
356CREATE_SIM_OBJECT(Iob)
357{
358    Iob::Params *p = new Iob::Params;
359    p->name = getInstanceName();
360    p->pio_delay = pio_latency;
361    p->platform = platform;
362    p->system = system;
363    return new Iob(p);
364}
365
366REGISTER_SIM_OBJECT("Iob", Iob)
367