iob.cc revision 8229
12810SN/A/* 212724Snikos.nikoleris@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68856Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78856Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88856Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98856Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108856Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118856Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128856Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138856Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Ali Saidi 292810SN/A */ 302810SN/A 312810SN/A/** @file 322810SN/A * This device implemetns the niagara I/O bridge chip. It manages incomming 332810SN/A * interrupts and posts them to the CPU when needed. It holds mask registers and 342810SN/A * various status registers for CPUs to check what interrupts are pending as 352810SN/A * well as facilities to send IPIs to other cpus. 362810SN/A */ 372810SN/A 382810SN/A#include <cstring> 392810SN/A 402810SN/A#include "arch/sparc/faults.hh" 414458SN/A#include "arch/sparc/isa_traits.hh" 424458SN/A#include "base/bitfield.hh" 4312724Snikos.nikoleris@arm.com#include "base/trace.hh" 4412724Snikos.nikoleris@arm.com#include "cpu/intr_control.hh" 452810SN/A#include "dev/sparc/iob.hh" 462810SN/A#include "dev/platform.hh" 472810SN/A#include "mem/packet_access.hh" 482810SN/A#include "mem/port.hh" 492810SN/A#include "sim/faults.hh" 502810SN/A#include "sim/system.hh" 512810SN/A 5211051Sandreas.hansson@arm.comIob::Iob(const Params *p) 5311051Sandreas.hansson@arm.com : PioDevice(p), ic(p->platform->intrctrl) 542810SN/A{ 5512724Snikos.nikoleris@arm.com iobManAddr = ULL(0x9800000000); 5612724Snikos.nikoleris@arm.com iobManSize = ULL(0x0100000000); 577676Snate@binkert.org iobJBusAddr = ULL(0x9F00000000); 582810SN/A iobJBusSize = ULL(0x0100000000); 5912724Snikos.nikoleris@arm.com assert (params()->system->threadContexts.size() <= MaxNiagaraProcs); 602810SN/A 612810SN/A pioDelay = p->pio_latency; 626215Snate@binkert.org 638232Snate@binkert.org // Get the interrupt controller from the platform 648232Snate@binkert.org ic = platform->intrctrl; 6512724Snikos.nikoleris@arm.com 6613223Sodanrc@yahoo.com.br for (int x = 0; x < NumDeviceIds; ++x) { 6713945Sodanrc@yahoo.com.br intMan[x].cpu = 0; 685338Sstever@gmail.com intMan[x].vector = 0; 6912724Snikos.nikoleris@arm.com intCtl[x].mask = true; 7011375Sandreas.hansson@arm.com intCtl[x].pend = false; 7112724Snikos.nikoleris@arm.com } 722810SN/A 7312724Snikos.nikoleris@arm.com} 748914Sandreas.hansson@arm.com 758229Snate@binkert.orgTick 7613352Snikos.nikoleris@arm.comIob::read(PacketPtr pkt) 7713892Sgabeblack@google.com{ 782811SN/A 7913416Sjavier.bueno@metempsy.com if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize) 8012724Snikos.nikoleris@arm.com readIob(pkt); 814626SN/A else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize) 828833Sdam.sunwoo@arm.com readJBus(pkt); 832810SN/A else 8412724Snikos.nikoleris@arm.com panic("Invalid address reached Iob\n"); 8512724Snikos.nikoleris@arm.com 8612724Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 8712724Snikos.nikoleris@arm.com return pioDelay; 8812724Snikos.nikoleris@arm.com} 8912724Snikos.nikoleris@arm.com 9012724Snikos.nikoleris@arm.comvoid 9112724Snikos.nikoleris@arm.comIob::readIob(PacketPtr pkt) 922810SN/A{ 932810SN/A Addr accessAddr = pkt->getAddr() - iobManAddr; 942810SN/A 9513892Sgabeblack@google.com if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) { 962810SN/A int index = (accessAddr - IntManAddr) >> 3; 9711375Sandreas.hansson@arm.com uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0; 984628SN/A pkt->set(data); 994628SN/A return; 1004628SN/A } 1014628SN/A 1024628SN/A if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) { 1034628SN/A int index = (accessAddr - IntCtlAddr) >> 3; 1044628SN/A uint64_t data = intCtl[index].mask ? 1 << 2 : 0 | 1054628SN/A intCtl[index].pend ? 1 << 0 : 0; 1068737Skoansin.tan@gmail.com pkt->set(data); 1074628SN/A return; 1084628SN/A } 1094628SN/A 1104628SN/A if (accessAddr == JIntVecAddr) { 1114628SN/A pkt->set(jIntVec); 1124628SN/A return; 1134628SN/A } 1144628SN/A 1154628SN/A panic("Read to unknown IOB offset 0x%x\n", accessAddr); 1164628SN/A} 1178737Skoansin.tan@gmail.com 1184628SN/Avoid 1198856Sandreas.hansson@arm.comIob::readJBus(PacketPtr pkt) 1208856Sandreas.hansson@arm.com{ 1218856Sandreas.hansson@arm.com Addr accessAddr = pkt->getAddr() - iobJBusAddr; 1228856Sandreas.hansson@arm.com int cpuid = pkt->req->contextId(); 1238856Sandreas.hansson@arm.com int index; 12410942Sandreas.hansson@arm.com uint64_t data; 1258856Sandreas.hansson@arm.com 1268856Sandreas.hansson@arm.com 1278856Sandreas.hansson@arm.com 1288922Swilliam.wang@arm.com 1292810SN/A if (accessAddr >= JIntData0Addr && accessAddr < JIntData1Addr) { 1308856Sandreas.hansson@arm.com index = (accessAddr - JIntData0Addr) >> 3; 1312844SN/A pkt->set(jBusData0[index]); 1328856Sandreas.hansson@arm.com return; 1338856Sandreas.hansson@arm.com } 1348856Sandreas.hansson@arm.com 13510713Sandreas.hansson@arm.com if (accessAddr >= JIntData1Addr && accessAddr < JIntDataA0Addr) { 1368856Sandreas.hansson@arm.com index = (accessAddr - JIntData1Addr) >> 3; 13710942Sandreas.hansson@arm.com pkt->set(jBusData1[index]); 1388856Sandreas.hansson@arm.com return; 13910942Sandreas.hansson@arm.com } 14010713Sandreas.hansson@arm.com 1418856Sandreas.hansson@arm.com if (accessAddr == JIntDataA0Addr) { 1428856Sandreas.hansson@arm.com pkt->set(jBusData0[cpuid]); 1433738SN/A return; 1444458SN/A } 1458856Sandreas.hansson@arm.com 14610713Sandreas.hansson@arm.com if (accessAddr == JIntDataA1Addr) { 14710713Sandreas.hansson@arm.com pkt->set(jBusData1[cpuid]); 14810713Sandreas.hansson@arm.com return; 1498914Sandreas.hansson@arm.com } 1502810SN/A 1518856Sandreas.hansson@arm.com if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) { 1528856Sandreas.hansson@arm.com index = (accessAddr - JIntBusyAddr) >> 3; 1538856Sandreas.hansson@arm.com data = jIntBusy[index].busy ? 1 << 5 : 0 | 1548914Sandreas.hansson@arm.com jIntBusy[index].source; 1558856Sandreas.hansson@arm.com pkt->set(data); 1568922Swilliam.wang@arm.com return; 1578856Sandreas.hansson@arm.com } 1583013SN/A if (accessAddr == JIntABusyAddr) { 1598856Sandreas.hansson@arm.com data = jIntBusy[cpuid].busy ? 1 << 5 : 0 | 16012724Snikos.nikoleris@arm.com jIntBusy[cpuid].source; 16112724Snikos.nikoleris@arm.com pkt->set(data); 16212724Snikos.nikoleris@arm.com return; 16312724Snikos.nikoleris@arm.com }; 16412724Snikos.nikoleris@arm.com 16512724Snikos.nikoleris@arm.com panic("Read to unknown JBus offset 0x%x\n", accessAddr); 16612724Snikos.nikoleris@arm.com} 16712724Snikos.nikoleris@arm.com 16812724Snikos.nikoleris@arm.comTick 16912724Snikos.nikoleris@arm.comIob::write(PacketPtr pkt) 17012724Snikos.nikoleris@arm.com{ 17112724Snikos.nikoleris@arm.com if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize) 17212724Snikos.nikoleris@arm.com writeIob(pkt); 17312724Snikos.nikoleris@arm.com else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize) 17412724Snikos.nikoleris@arm.com writeJBus(pkt); 17512724Snikos.nikoleris@arm.com else 17612724Snikos.nikoleris@arm.com panic("Invalid address reached Iob\n"); 17712724Snikos.nikoleris@arm.com 17812724Snikos.nikoleris@arm.com 17912724Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 18012724Snikos.nikoleris@arm.com return pioDelay; 18112724Snikos.nikoleris@arm.com} 18212724Snikos.nikoleris@arm.com 18312724Snikos.nikoleris@arm.comvoid 18412724Snikos.nikoleris@arm.comIob::writeIob(PacketPtr pkt) 18512724Snikos.nikoleris@arm.com{ 18612724Snikos.nikoleris@arm.com Addr accessAddr = pkt->getAddr() - iobManAddr; 18712724Snikos.nikoleris@arm.com int index; 18812724Snikos.nikoleris@arm.com uint64_t data; 18912724Snikos.nikoleris@arm.com 19012724Snikos.nikoleris@arm.com if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) { 19112724Snikos.nikoleris@arm.com index = (accessAddr - IntManAddr) >> 3; 19212724Snikos.nikoleris@arm.com data = pkt->get<uint64_t>(); 19313860Sodanrc@yahoo.com.br intMan[index].cpu = bits(data,12,8); 19413860Sodanrc@yahoo.com.br intMan[index].vector = bits(data,5,0); 19512724Snikos.nikoleris@arm.com DPRINTF(Iob, "Wrote IntMan %d cpu %d, vec %d\n", index, 19613860Sodanrc@yahoo.com.br intMan[index].cpu, intMan[index].vector); 19712724Snikos.nikoleris@arm.com return; 19813860Sodanrc@yahoo.com.br } 19912724Snikos.nikoleris@arm.com 20012724Snikos.nikoleris@arm.com if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) { 20112724Snikos.nikoleris@arm.com index = (accessAddr - IntCtlAddr) >> 3; 20212724Snikos.nikoleris@arm.com data = pkt->get<uint64_t>(); 20312724Snikos.nikoleris@arm.com intCtl[index].mask = bits(data,2,2); 20412724Snikos.nikoleris@arm.com if (bits(data,1,1)) 20512724Snikos.nikoleris@arm.com intCtl[index].pend = false; 20612724Snikos.nikoleris@arm.com DPRINTF(Iob, "Wrote IntCtl %d pend %d cleared %d\n", index, 20712724Snikos.nikoleris@arm.com intCtl[index].pend, bits(data,2,2)); 20812724Snikos.nikoleris@arm.com return; 20912724Snikos.nikoleris@arm.com } 21012724Snikos.nikoleris@arm.com 21112724Snikos.nikoleris@arm.com if (accessAddr == JIntVecAddr) { 21212724Snikos.nikoleris@arm.com jIntVec = bits(pkt->get<uint64_t>(), 5,0); 21312724Snikos.nikoleris@arm.com DPRINTF(Iob, "Wrote jIntVec %d\n", jIntVec); 21412724Snikos.nikoleris@arm.com return; 21512724Snikos.nikoleris@arm.com } 21612724Snikos.nikoleris@arm.com 21712724Snikos.nikoleris@arm.com if (accessAddr >= IntVecDisAddr && accessAddr < IntVecDisAddr + IntVecDisSize) { 21812724Snikos.nikoleris@arm.com Type type; 21912724Snikos.nikoleris@arm.com int cpu_id; 22012724Snikos.nikoleris@arm.com int vector; 22112724Snikos.nikoleris@arm.com index = (accessAddr - IntManAddr) >> 3; 22212724Snikos.nikoleris@arm.com data = pkt->get<uint64_t>(); 22312724Snikos.nikoleris@arm.com type = (Type)bits(data,17,16); 22412724Snikos.nikoleris@arm.com cpu_id = bits(data, 12,8); 22512724Snikos.nikoleris@arm.com vector = bits(data,5,0); 22612724Snikos.nikoleris@arm.com generateIpi(type,cpu_id, vector); 22712724Snikos.nikoleris@arm.com return; 22812724Snikos.nikoleris@arm.com } 22912724Snikos.nikoleris@arm.com 23012724Snikos.nikoleris@arm.com panic("Write to unknown IOB offset 0x%x\n", accessAddr); 23112724Snikos.nikoleris@arm.com} 23212724Snikos.nikoleris@arm.com 23312724Snikos.nikoleris@arm.comvoid 23412724Snikos.nikoleris@arm.comIob::writeJBus(PacketPtr pkt) 23512724Snikos.nikoleris@arm.com{ 23612724Snikos.nikoleris@arm.com Addr accessAddr = pkt->getAddr() - iobJBusAddr; 23712724Snikos.nikoleris@arm.com int cpuid = pkt->req->contextId(); 23812724Snikos.nikoleris@arm.com int index; 23912724Snikos.nikoleris@arm.com uint64_t data; 24012724Snikos.nikoleris@arm.com 24112724Snikos.nikoleris@arm.com if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) { 24212724Snikos.nikoleris@arm.com index = (accessAddr - JIntBusyAddr) >> 3; 2438856Sandreas.hansson@arm.com data = pkt->get<uint64_t>(); 2448856Sandreas.hansson@arm.com jIntBusy[index].busy = bits(data,5,5); 2458856Sandreas.hansson@arm.com DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", index, 2468856Sandreas.hansson@arm.com jIntBusy[index].busy); 2478856Sandreas.hansson@arm.com return; 2488856Sandreas.hansson@arm.com } 2498856Sandreas.hansson@arm.com if (accessAddr == JIntABusyAddr) { 2508922Swilliam.wang@arm.com data = pkt->get<uint64_t>(); 2518856Sandreas.hansson@arm.com jIntBusy[cpuid].busy = bits(data,5,5); 2525314SN/A DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", cpuid, 2532811SN/A jIntBusy[cpuid].busy); 2548856Sandreas.hansson@arm.com return; 2558856Sandreas.hansson@arm.com }; 2562810SN/A 2572810SN/A panic("Write to unknown JBus offset 0x%x\n", accessAddr); 2588856Sandreas.hansson@arm.com} 2592810SN/A 2602810SN/Avoid 26110345SCurtis.Dunham@arm.comIob::receiveDeviceInterrupt(DeviceId devid) 26210345SCurtis.Dunham@arm.com{ 2638856Sandreas.hansson@arm.com assert(devid < NumDeviceIds); 2648856Sandreas.hansson@arm.com if (intCtl[devid].mask) 2658856Sandreas.hansson@arm.com return; 2668856Sandreas.hansson@arm.com intCtl[devid].mask = true; 2673606SN/A intCtl[devid].pend = true; 2688914Sandreas.hansson@arm.com DPRINTF(Iob, "Receiving Device interrupt: %d for cpu %d vec %d\n", 26910713Sandreas.hansson@arm.com devid, intMan[devid].cpu, intMan[devid].vector); 2708914Sandreas.hansson@arm.com ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector); 2712810SN/A} 2722810SN/A 2732897SN/A 2742897SN/Avoid 2758856Sandreas.hansson@arm.comIob::generateIpi(Type type, int cpu_id, int vector) 2764458SN/A{ 27710344Sandreas.hansson@arm.com SparcISA::SparcFault<SparcISA::PowerOnReset> *por = new SparcISA::PowerOnReset(); 27810344Sandreas.hansson@arm.com if (cpu_id >= sys->numContexts()) 27912084Sspwilson2@wisc.edu return; 2808856Sandreas.hansson@arm.com 2812811SN/A switch (type) { 2822810SN/A case 0: // interrupt 28312724Snikos.nikoleris@arm.com DPRINTF(Iob, "Generating interrupt because of I/O write to cpu: %d vec %d\n", 28412724Snikos.nikoleris@arm.com cpu_id, vector); 28512724Snikos.nikoleris@arm.com ic->post(cpu_id, SparcISA::IT_INT_VEC, vector); 28612724Snikos.nikoleris@arm.com break; 28712724Snikos.nikoleris@arm.com case 1: // reset 28812724Snikos.nikoleris@arm.com warn("Sending reset to CPU: %d\n", cpu_id); 28912724Snikos.nikoleris@arm.com if (vector != por->trapType()) 29012724Snikos.nikoleris@arm.com panic("Don't know how to set non-POR reset to cpu\n"); 29112724Snikos.nikoleris@arm.com por->invoke(sys->threadContexts[cpu_id]); 29212724Snikos.nikoleris@arm.com sys->threadContexts[cpu_id]->activate(); 29312724Snikos.nikoleris@arm.com break; 29412724Snikos.nikoleris@arm.com case 2: // idle -- this means stop executing and don't wake on interrupts 29512724Snikos.nikoleris@arm.com DPRINTF(Iob, "Idling CPU because of I/O write cpu: %d\n", cpu_id); 29612724Snikos.nikoleris@arm.com sys->threadContexts[cpu_id]->halt(); 29712724Snikos.nikoleris@arm.com break; 29812724Snikos.nikoleris@arm.com case 3: // resume 29912724Snikos.nikoleris@arm.com DPRINTF(Iob, "Resuming CPU because of I/O write cpu: %d\n", cpu_id); 30012724Snikos.nikoleris@arm.com sys->threadContexts[cpu_id]->activate(); 30112724Snikos.nikoleris@arm.com break; 30212724Snikos.nikoleris@arm.com default: 30312724Snikos.nikoleris@arm.com panic("Invalid type to generate ipi\n"); 30412724Snikos.nikoleris@arm.com } 30512724Snikos.nikoleris@arm.com} 30612724Snikos.nikoleris@arm.com 30712724Snikos.nikoleris@arm.combool 30812724Snikos.nikoleris@arm.comIob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1) 30912724Snikos.nikoleris@arm.com{ 31012724Snikos.nikoleris@arm.com // If we are already dealing with an interrupt for that cpu we can't deal 31112724Snikos.nikoleris@arm.com // with another one right now... come back later 31212724Snikos.nikoleris@arm.com if (jIntBusy[cpu_id].busy) 31312724Snikos.nikoleris@arm.com return false; 31412724Snikos.nikoleris@arm.com 31512724Snikos.nikoleris@arm.com DPRINTF(Iob, "Receiving jBus interrupt: %d for cpu %d vec %d\n", 3163338SN/A source, cpu_id, jIntVec); 3174626SN/A 3184626SN/A jIntBusy[cpu_id].busy = true; 3194626SN/A jIntBusy[cpu_id].source = source; 3204626SN/A jBusData0[cpu_id] = d0; 3214626SN/A jBusData1[cpu_id] = d1; 3224626SN/A 32311375Sandreas.hansson@arm.com ic->post(cpu_id, SparcISA::IT_INT_VEC, jIntVec); 3244626SN/A return true; 32512724Snikos.nikoleris@arm.com} 32612724Snikos.nikoleris@arm.com 32712724Snikos.nikoleris@arm.comvoid 32813945Sodanrc@yahoo.com.brIob::addressRanges(AddrRangeList &range_list) 32913945Sodanrc@yahoo.com.br{ 33013945Sodanrc@yahoo.com.br range_list.clear(); 33112724Snikos.nikoleris@arm.com range_list.push_back(RangeSize(iobManAddr, iobManSize)); 33212724Snikos.nikoleris@arm.com range_list.push_back(RangeSize(iobJBusAddr, iobJBusSize)); 33312724Snikos.nikoleris@arm.com} 33413416Sjavier.bueno@metempsy.com 33513416Sjavier.bueno@metempsy.com 33613416Sjavier.bueno@metempsy.comvoid 33713416Sjavier.bueno@metempsy.comIob::serialize(std::ostream &os) 33813416Sjavier.bueno@metempsy.com{ 33912724Snikos.nikoleris@arm.com 34013717Sivan.pizarro@metempsy.com SERIALIZE_SCALAR(jIntVec); 34113717Sivan.pizarro@metempsy.com SERIALIZE_ARRAY(jBusData0, MaxNiagaraProcs); 34213717Sivan.pizarro@metempsy.com SERIALIZE_ARRAY(jBusData1, MaxNiagaraProcs); 34312724Snikos.nikoleris@arm.com for (int x = 0; x < NumDeviceIds; x++) { 34413352Snikos.nikoleris@arm.com nameOut(os, csprintf("%s.Int%d", name(), x)); 34513352Snikos.nikoleris@arm.com paramOut(os, "cpu", intMan[x].cpu); 34613352Snikos.nikoleris@arm.com paramOut(os, "vector", intMan[x].vector); 34713352Snikos.nikoleris@arm.com paramOut(os, "mask", intCtl[x].mask); 34813352Snikos.nikoleris@arm.com paramOut(os, "pend", intCtl[x].pend); 34913352Snikos.nikoleris@arm.com }; 35013352Snikos.nikoleris@arm.com for (int x = 0; x < MaxNiagaraProcs; x++) { 35113352Snikos.nikoleris@arm.com nameOut(os, csprintf("%s.jIntBusy%d", name(), x)); 35213352Snikos.nikoleris@arm.com paramOut(os, "busy", jIntBusy[x].busy); 35313352Snikos.nikoleris@arm.com paramOut(os, "source", jIntBusy[x].source); 35413352Snikos.nikoleris@arm.com }; 35513352Snikos.nikoleris@arm.com} 35613352Snikos.nikoleris@arm.com 35713352Snikos.nikoleris@arm.comvoid 35813352Snikos.nikoleris@arm.comIob::unserialize(Checkpoint *cp, const std::string §ion) 35913352Snikos.nikoleris@arm.com{ 36012724Snikos.nikoleris@arm.com UNSERIALIZE_SCALAR(jIntVec); 36112724Snikos.nikoleris@arm.com UNSERIALIZE_ARRAY(jBusData0, MaxNiagaraProcs); 36212724Snikos.nikoleris@arm.com UNSERIALIZE_ARRAY(jBusData1, MaxNiagaraProcs); 36312724Snikos.nikoleris@arm.com for (int x = 0; x < NumDeviceIds; x++) { 36412724Snikos.nikoleris@arm.com paramIn(cp, csprintf("%s.Int%d", name(), x), "cpu", intMan[x].cpu); 36512730Sodanrc@yahoo.com.br paramIn(cp, csprintf("%s.Int%d", name(), x), "vector", intMan[x].vector); 36612724Snikos.nikoleris@arm.com paramIn(cp, csprintf("%s.Int%d", name(), x), "mask", intCtl[x].mask); 36712724Snikos.nikoleris@arm.com paramIn(cp, csprintf("%s.Int%d", name(), x), "pend", intCtl[x].pend); 36812724Snikos.nikoleris@arm.com }; 36912724Snikos.nikoleris@arm.com for (int x = 0; x < MaxNiagaraProcs; x++) { 37012724Snikos.nikoleris@arm.com paramIn(cp, csprintf("%s.jIntBusy%d", name(), x), "busy", jIntBusy[x].busy); 37112724Snikos.nikoleris@arm.com paramIn(cp, csprintf("%s.jIntBusy%d", name(), x), "source", jIntBusy[x].source); 37212724Snikos.nikoleris@arm.com }; 37310693SMarco.Balboni@ARM.com} 37411375Sandreas.hansson@arm.com 37511375Sandreas.hansson@arm.comIob * 37610693SMarco.Balboni@ARM.comIobParams::create() 37711375Sandreas.hansson@arm.com{ 3784628SN/A return new Iob(this); 37911375Sandreas.hansson@arm.com} 38011375Sandreas.hansson@arm.com