T1000.py revision 8847:ef8630054b5e 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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5# modification, are permitted provided that the following conditions are
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8# redistributions in binary form must reproduce the above copyright
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Gabe Black
28
29from m5.params import *
30from m5.proxy import *
31from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
32from Platform import Platform
33from Terminal import Terminal
34from Uart import Uart8250
35
36
37class MmDisk(BasicPioDevice):
38    type = 'MmDisk'
39    image = Param.DiskImage("Disk Image")
40    pio_addr = 0x1F40000000
41
42class DumbTOD(BasicPioDevice):
43    type = 'DumbTOD'
44    time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
45    pio_addr = 0xfff0c1fff8
46
47class Iob(PioDevice):
48    type = 'Iob'
49    platform = Param.Platform(Parent.any, "Platform this device is part of.")
50    pio_latency = Param.Latency('1ns', "Programed IO latency in simticks")
51
52
53class T1000(Platform):
54    type = 'T1000'
55    system = Param.System(Parent.any, "system")
56
57    fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
58            #warn_access="Accessing Clock Unit -- Unimplemented!")
59
60    fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
61            ret_data64=0x0000000000000000, update_data=False)
62            #warn_access="Accessing Memory Banks -- Unimplemented!")
63
64    fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
65            #warn_access="Accessing JBI -- Unimplemented!")
66
67    fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
68            ret_data64=0x0000000000000001, update_data=True)
69            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
70
71    fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
72            ret_data64=0x0000000000000001, update_data=True)
73            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
74
75    fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
76            ret_data64=0x0000000000000001, update_data=True)
77            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
78
79    fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
80            ret_data64=0x0000000000000001, update_data=True)
81            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
82
83    fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
84            ret_data64=0x0000000000000000, update_data=True)
85            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
86
87    fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
88            ret_data64=0x0000000000000000, update_data=True)
89            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
90
91    fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
92            ret_data64=0x0000000000000000, update_data=True)
93            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
94
95    fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
96            ret_data64=0x0000000000000000, update_data=True)
97            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
98
99    fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
100            #warn_access="Accessing SSI -- Unimplemented!")
101
102    hterm = Terminal()
103    hvuart = Uart8250(pio_addr=0xfff0c2c000)
104    htod = DumbTOD()
105
106    pterm = Terminal()
107    puart0 = Uart8250(pio_addr=0x1f10000000)
108
109    iob = Iob()
110    # Attach I/O devices that are on chip
111    def attachOnChipIO(self, bus):
112        self.iob.pio = bus.master
113        self.htod.pio = bus.master
114
115
116    # Attach I/O devices to specified bus object.  Can't do this
117    # earlier, since the bus object itself is typically defined at the
118    # System level.
119    def attachIO(self, bus):
120        self.hvuart.terminal = self.hterm
121        self.puart0.terminal = self.pterm
122        self.fake_clk.pio = bus.master
123        self.fake_membnks.pio = bus.master
124        self.fake_l2_1.pio = bus.master
125        self.fake_l2_2.pio = bus.master
126        self.fake_l2_3.pio = bus.master
127        self.fake_l2_4.pio = bus.master
128        self.fake_l2esr_1.pio = bus.master
129        self.fake_l2esr_2.pio = bus.master
130        self.fake_l2esr_3.pio = bus.master
131        self.fake_l2esr_4.pio = bus.master
132        self.fake_ssi.pio = bus.master
133        self.fake_jbi.pio = bus.master
134        self.puart0.pio = bus.master
135        self.hvuart.pio = bus.master
136